Lines Matching refs:spi
19 #include <linux/spi/spi.h>
244 int (*get_fifo_size)(struct stm32_spi *spi);
245 int (*get_bpw_mask)(struct stm32_spi *spi);
246 void (*disable)(struct stm32_spi *spi);
247 int (*config)(struct stm32_spi *spi);
248 void (*set_bpw)(struct stm32_spi *spi);
249 int (*set_mode)(struct stm32_spi *spi, unsigned int comm_type);
250 void (*set_data_idleness)(struct stm32_spi *spi, u32 length);
251 int (*set_number_of_data)(struct stm32_spi *spi, u32 length);
252 void (*transfer_one_dma_start)(struct stm32_spi *spi);
255 int (*transfer_one_irq)(struct stm32_spi *spi);
353 static inline void stm32_spi_set_bits(struct stm32_spi *spi,
356 writel_relaxed(readl_relaxed(spi->base + offset) | bits,
357 spi->base + offset);
360 static inline void stm32_spi_clr_bits(struct stm32_spi *spi,
363 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits,
364 spi->base + offset);
369 * @spi: pointer to the spi controller data structure
371 static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi)
376 spin_lock_irqsave(&spi->lock, flags);
378 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
380 while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP)
381 writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR);
383 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
385 spin_unlock_irqrestore(&spi->lock, flags);
387 dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count);
394 * @spi: pointer to the spi controller data structure
396 static int stm32f4_spi_get_bpw_mask(struct stm32_spi *spi)
398 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n");
404 * @spi: pointer to the spi controller data structure
406 static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi)
411 spin_lock_irqsave(&spi->lock, flags);
417 stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE);
419 cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1);
424 spin_unlock_irqrestore(&spi->lock, flags);
426 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw);
433 * @spi: pointer to the spi controller data structure
440 static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
445 /* Ensure spi->clk_rate is even */
446 div = DIV_ROUND_CLOSEST(spi->clk_rate & ~0x1, speed_hz);
464 spi->cur_speed = spi->clk_rate / (1 << mbrdiv);
471 * @spi: pointer to the spi controller data structure
474 static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len)
479 half_fifo = (spi->fifo_size / 2);
487 if (spi->cur_bpw <= 8)
489 else if (spi->cur_bpw <= 16)
495 if (spi->cur_bpw > 8)
508 * @spi: pointer to the spi controller data structure
513 static void stm32f4_spi_write_tx(struct stm32_spi *spi)
515 if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
517 u32 offs = spi->cur_xferlen - spi->tx_len;
519 if (spi->cur_bpw == 16) {
520 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
522 writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR);
523 spi->tx_len -= sizeof(u16);
525 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
527 writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR);
528 spi->tx_len -= sizeof(u8);
532 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
537 * @spi: pointer to the spi controller data structure
542 static void stm32h7_spi_write_txfifo(struct stm32_spi *spi)
544 while ((spi->tx_len > 0) &&
545 (readl_relaxed(spi->base + STM32H7_SPI_SR) &
547 u32 offs = spi->cur_xferlen - spi->tx_len;
549 if (spi->tx_len >= sizeof(u32)) {
550 const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs);
552 writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR);
553 spi->tx_len -= sizeof(u32);
554 } else if (spi->tx_len >= sizeof(u16)) {
555 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
557 writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR);
558 spi->tx_len -= sizeof(u16);
560 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
562 writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR);
563 spi->tx_len -= sizeof(u8);
567 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
572 * @spi: pointer to the spi controller data structure
577 static void stm32f4_spi_read_rx(struct stm32_spi *spi)
579 if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
581 u32 offs = spi->cur_xferlen - spi->rx_len;
583 if (spi->cur_bpw == 16) {
584 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
586 *rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR);
587 spi->rx_len -= sizeof(u16);
589 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
591 *rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR);
592 spi->rx_len -= sizeof(u8);
596 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len);
601 * @spi: pointer to the spi controller data structure
607 static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
609 u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
613 while ((spi->rx_len > 0) &&
616 u32 offs = spi->cur_xferlen - spi->rx_len;
618 if ((spi->rx_len >= sizeof(u32)) ||
620 u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs);
622 *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR);
623 spi->rx_len -= sizeof(u32);
624 } else if ((spi->rx_len >= sizeof(u16)) ||
625 (flush && (rxplvl >= 2 || spi->cur_bpw > 8))) {
626 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
628 *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR);
629 spi->rx_len -= sizeof(u16);
631 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
633 *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR);
634 spi->rx_len -= sizeof(u8);
637 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
642 dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__,
643 flush ? "(flush)" : "", spi->rx_len);
648 * @spi: pointer to the spi controller data structure
650 static void stm32_spi_enable(struct stm32_spi *spi)
652 dev_dbg(spi->dev, "enable controller\n");
654 stm32_spi_set_bits(spi, spi->cfg->regs->en.reg,
655 spi->cfg->regs->en.mask);
660 * @spi: pointer to the spi controller data structure
662 static void stm32f4_spi_disable(struct stm32_spi *spi)
667 dev_dbg(spi->dev, "disable controller\n");
669 spin_lock_irqsave(&spi->lock, flags);
671 if (!(readl_relaxed(spi->base + STM32F4_SPI_CR1) &
673 spin_unlock_irqrestore(&spi->lock, flags);
678 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXEIE |
683 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32F4_SPI_SR,
686 dev_warn(spi->dev, "disabling condition timeout\n");
689 if (spi->cur_usedma && spi->dma_tx)
690 dmaengine_terminate_all(spi->dma_tx);
691 if (spi->cur_usedma && spi->dma_rx)
692 dmaengine_terminate_all(spi->dma_rx);
694 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE);
696 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN |
700 readl_relaxed(spi->base + STM32F4_SPI_DR);
701 readl_relaxed(spi->base + STM32F4_SPI_SR);
703 spin_unlock_irqrestore(&spi->lock, flags);
708 * @spi: pointer to the spi controller data structure
718 static void stm32h7_spi_disable(struct stm32_spi *spi)
723 dev_dbg(spi->dev, "disable controller\n");
725 spin_lock_irqsave(&spi->lock, flags);
727 cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1);
730 spin_unlock_irqrestore(&spi->lock, flags);
735 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32H7_SPI_SR,
740 spi->base + STM32H7_SPI_CR1);
742 spi->base + STM32H7_SPI_SR,
745 dev_warn(spi->dev,
750 if (!spi->cur_usedma && spi->rx_buf && (spi->rx_len > 0))
751 stm32h7_spi_read_rxfifo(spi, true);
753 if (spi->cur_usedma && spi->dma_tx)
754 dmaengine_terminate_all(spi->dma_tx);
755 if (spi->cur_usedma && spi->dma_rx)
756 dmaengine_terminate_all(spi->dma_rx);
758 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
760 stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN |
764 writel_relaxed(0, spi->base + STM32H7_SPI_IER);
765 writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR);
767 spin_unlock_irqrestore(&spi->lock, flags);
773 * @spi_dev: pointer to the spi device
774 * @transfer: pointer to spi transfer
784 struct stm32_spi *spi = spi_master_get_devdata(master);
786 if (spi->cfg->has_fifo)
787 dma_size = spi->fifo_size;
791 dev_dbg(spi->dev, "%s: %s\n", __func__,
805 struct stm32_spi *spi = spi_master_get_devdata(master);
809 spin_lock(&spi->lock);
811 sr = readl_relaxed(spi->base + STM32F4_SPI_SR);
818 if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX ||
819 spi->cur_comm == SPI_3WIRE_TX)) {
825 if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX ||
826 spi->cur_comm == SPI_SIMPLEX_RX ||
827 spi->cur_comm == SPI_3WIRE_RX)) {
834 dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr);
835 spin_unlock(&spi->lock);
840 dev_warn(spi->dev, "Overrun: received value discarded\n");
843 readl_relaxed(spi->base + STM32F4_SPI_DR);
844 readl_relaxed(spi->base + STM32F4_SPI_SR);
856 if (spi->tx_buf)
857 stm32f4_spi_write_tx(spi);
858 if (spi->tx_len == 0)
863 stm32f4_spi_read_rx(spi);
864 if (spi->rx_len == 0)
866 else if (spi->tx_buf)/* Load data for discontinuous mode */
867 stm32f4_spi_write_tx(spi);
873 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2,
877 spin_unlock(&spi->lock);
881 spin_unlock(&spi->lock);
893 struct stm32_spi *spi = spi_master_get_devdata(master);
896 stm32f4_spi_disable(spi);
909 struct stm32_spi *spi = spi_master_get_devdata(master);
914 spin_lock_irqsave(&spi->lock, flags);
916 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
917 ier = readl_relaxed(spi->base + STM32H7_SPI_IER);
930 if ((spi->cur_comm == SPI_FULL_DUPLEX) && !spi->cur_usedma)
934 dev_warn(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
936 spin_unlock_irqrestore(&spi->lock, flags);
946 dev_dbg_ratelimited(spi->dev, "Communication suspended\n");
947 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
948 stm32h7_spi_read_rxfifo(spi, false);
953 if (spi->cur_usedma)
958 dev_warn(spi->dev, "Mode fault: transfer aborted\n");
963 dev_err(spi->dev, "Overrun: RX data lost\n");
968 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
969 stm32h7_spi_read_rxfifo(spi, true);
974 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0)))
975 stm32h7_spi_write_txfifo(spi);
978 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
979 stm32h7_spi_read_rxfifo(spi, false);
981 writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR);
983 spin_unlock_irqrestore(&spi->lock, flags);
986 stm32h7_spi_disable(spi);
996 * @msg: pointer to spi message
1001 struct stm32_spi *spi = spi_master_get_devdata(master);
1002 struct spi_device *spi_dev = msg->spi;
1008 spi->cur_midi = 0;
1009 if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi))
1010 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi);
1013 setb |= spi->cfg->regs->cpol.mask;
1015 clrb |= spi->cfg->regs->cpol.mask;
1018 setb |= spi->cfg->regs->cpha.mask;
1020 clrb |= spi->cfg->regs->cpha.mask;
1023 setb |= spi->cfg->regs->lsb_first.mask;
1025 clrb |= spi->cfg->regs->lsb_first.mask;
1027 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
1033 spin_lock_irqsave(&spi->lock, flags);
1038 (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) &
1040 spi->base + spi->cfg->regs->cpol.reg);
1042 spin_unlock_irqrestore(&spi->lock, flags);
1049 * @data: pointer to the spi controller data structure
1055 struct stm32_spi *spi = data;
1057 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1058 spi_finalize_current_transfer(spi->master);
1059 stm32f4_spi_disable(spi);
1065 * @data: pointer to the spi controller data structure
1071 struct stm32_spi *spi = data;
1073 spi_finalize_current_transfer(spi->master);
1074 stm32f4_spi_disable(spi);
1079 * @data: pointer to the spi controller data structure
1086 struct stm32_spi *spi = data;
1090 spin_lock_irqsave(&spi->lock, flags);
1092 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
1094 spin_unlock_irqrestore(&spi->lock, flags);
1097 dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr);
1105 * @spi: pointer to the spi controller data structure
1109 static void stm32_spi_dma_config(struct stm32_spi *spi,
1116 if (spi->cur_bpw <= 8)
1118 else if (spi->cur_bpw <= 16)
1123 if (spi->cfg->has_fifo) {
1125 if (spi->cur_fthlv == 2)
1128 maxburst = spi->cur_fthlv;
1136 dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg;
1140 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n",
1143 dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg;
1147 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n",
1155 * @spi: pointer to the spi controller data structure
1160 static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi)
1166 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1168 } else if (spi->cur_comm == SPI_FULL_DUPLEX ||
1169 spi->cur_comm == SPI_SIMPLEX_RX ||
1170 spi->cur_comm == SPI_3WIRE_RX) {
1180 spin_lock_irqsave(&spi->lock, flags);
1182 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, cr2);
1184 stm32_spi_enable(spi);
1187 if (spi->tx_buf)
1188 stm32f4_spi_write_tx(spi);
1190 spin_unlock_irqrestore(&spi->lock, flags);
1198 * @spi: pointer to the spi controller data structure
1203 static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi)
1209 if (spi->tx_buf && spi->rx_buf) /* Full Duplex */
1211 else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */
1213 else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */
1220 spin_lock_irqsave(&spi->lock, flags);
1222 stm32_spi_enable(spi);
1225 if (spi->tx_buf)
1226 stm32h7_spi_write_txfifo(spi);
1228 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1230 writel_relaxed(ier, spi->base + STM32H7_SPI_IER);
1232 spin_unlock_irqrestore(&spi->lock, flags);
1240 * @spi: pointer to the spi controller data structure
1242 static void stm32f4_spi_transfer_one_dma_start(struct stm32_spi *spi)
1245 if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX ||
1246 spi->cur_comm == SPI_FULL_DUPLEX) {
1252 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_ERRIE);
1255 stm32_spi_enable(spi);
1261 * @spi: pointer to the spi controller data structure
1263 static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi)
1266 stm32_spi_set_bits(spi, STM32H7_SPI_IER, STM32H7_SPI_IER_EOTIE |
1271 stm32_spi_enable(spi);
1273 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1278 * @spi: pointer to the spi controller data structure
1284 static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
1291 spin_lock_irqsave(&spi->lock, flags);
1294 if (spi->rx_buf && spi->dma_rx) {
1295 stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM);
1296 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf);
1299 stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1300 spi->cfg->regs->dma_rx_en.mask);
1303 spi->dma_rx, xfer->rx_sg.sgl,
1310 if (spi->tx_buf && spi->dma_tx) {
1311 stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV);
1312 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf);
1315 spi->dma_tx, xfer->tx_sg.sgl,
1321 if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) ||
1322 (spi->rx_buf && spi->dma_rx && !rx_dma_desc))
1325 if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc))
1329 rx_dma_desc->callback = spi->cfg->dma_rx_cb;
1330 rx_dma_desc->callback_param = spi;
1333 dev_err(spi->dev, "Rx DMA submit failed\n");
1337 dma_async_issue_pending(spi->dma_rx);
1341 if (spi->cur_comm == SPI_SIMPLEX_TX ||
1342 spi->cur_comm == SPI_3WIRE_TX) {
1343 tx_dma_desc->callback = spi->cfg->dma_tx_cb;
1344 tx_dma_desc->callback_param = spi;
1348 dev_err(spi->dev, "Tx DMA submit failed\n");
1352 dma_async_issue_pending(spi->dma_tx);
1355 stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg,
1356 spi->cfg->regs->dma_tx_en.mask);
1359 spi->cfg->transfer_one_dma_start(spi);
1361 spin_unlock_irqrestore(&spi->lock, flags);
1366 if (spi->dma_rx)
1367 dmaengine_terminate_all(spi->dma_rx);
1370 stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1371 spi->cfg->regs->dma_rx_en.mask);
1373 spin_unlock_irqrestore(&spi->lock, flags);
1375 dev_info(spi->dev, "DMA issue: fall back to irq transfer\n");
1377 spi->cur_usedma = false;
1378 return spi->cfg->transfer_one_irq(spi);
1383 * @spi: pointer to the spi controller data structure
1385 static void stm32f4_spi_set_bpw(struct stm32_spi *spi)
1387 if (spi->cur_bpw == 16)
1388 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
1390 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
1395 * @spi: pointer to the spi controller data structure
1397 static void stm32h7_spi_set_bpw(struct stm32_spi *spi)
1402 bpw = spi->cur_bpw - 1;
1408 spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
1409 fthlv = spi->cur_fthlv - 1;
1416 (readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
1418 spi->base + STM32H7_SPI_CFG1);
1423 * @spi: pointer to the spi controller data structure
1426 static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv)
1430 clrb |= spi->cfg->regs->br.mask;
1431 setb |= ((u32)mbrdiv << spi->cfg->regs->br.shift) &
1432 spi->cfg->regs->br.mask;
1434 writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) &
1436 spi->base + spi->cfg->regs->br.reg);
1441 * @spi_dev: pointer to the spi device
1442 * @transfer: pointer to spi transfer
1472 * @spi: pointer to the spi controller data structure
1475 static int stm32f4_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
1478 stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
1483 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
1487 stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
1489 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
1500 * @spi: pointer to the spi controller data structure
1503 static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
1510 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1513 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1527 (readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1529 spi->base + STM32H7_SPI_CFG2);
1537 * @spi: pointer to the spi controller data structure
1540 static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len)
1545 if ((len > 1) && (spi->cur_midi > 0)) {
1546 u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed);
1547 u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
1551 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
1557 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1559 spi->base + STM32H7_SPI_CFG2);
1564 * @spi: pointer to the spi controller data structure
1567 static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words)
1575 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CR2) &
1577 spi->base + STM32H7_SPI_CR2);
1589 * @spi: pointer to the spi controller data structure
1590 * @spi_dev: pointer to the spi device
1591 * @transfer: pointer to spi transfer
1593 static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
1602 spin_lock_irqsave(&spi->lock, flags);
1604 spi->cur_xferlen = transfer->len;
1606 spi->cur_bpw = transfer->bits_per_word;
1607 spi->cfg->set_bpw(spi);
1609 /* Update spi->cur_speed with real clock speed */
1610 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz,
1611 spi->cfg->baud_rate_div_min,
1612 spi->cfg->baud_rate_div_max);
1618 transfer->speed_hz = spi->cur_speed;
1619 stm32_spi_set_mbr(spi, mbr);
1622 ret = spi->cfg->set_mode(spi, comm_type);
1626 spi->cur_comm = comm_type;
1628 if (spi->cfg->set_data_idleness)
1629 spi->cfg->set_data_idleness(spi, transfer->len);
1631 if (spi->cur_bpw <= 8)
1633 else if (spi->cur_bpw <= 16)
1638 if (spi->cfg->set_number_of_data) {
1639 ret = spi->cfg->set_number_of_data(spi, nb_words);
1644 dev_dbg(spi->dev, "transfer communication mode set to %d\n",
1645 spi->cur_comm);
1646 dev_dbg(spi->dev,
1648 spi->cur_bpw, spi->cur_fthlv);
1649 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed);
1650 dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n",
1651 spi->cur_xferlen, nb_words);
1652 dev_dbg(spi->dev, "dma %s\n",
1653 (spi->cur_usedma) ? "enabled" : "disabled");
1656 spin_unlock_irqrestore(&spi->lock, flags);
1664 * @spi_dev: pointer to the spi device
1665 * @transfer: pointer to spi transfer
1674 struct stm32_spi *spi = spi_master_get_devdata(master);
1681 spi->tx_buf = transfer->tx_buf;
1682 spi->rx_buf = transfer->rx_buf;
1683 spi->tx_len = spi->tx_buf ? transfer->len : 0;
1684 spi->rx_len = spi->rx_buf ? transfer->len : 0;
1686 spi->cur_usedma = (master->can_dma &&
1689 ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer);
1691 dev_err(spi->dev, "SPI transfer setup failed\n");
1695 if (spi->cur_usedma)
1696 return stm32_spi_transfer_one_dma(spi, transfer);
1698 return spi->cfg->transfer_one_irq(spi);
1704 * @msg: pointer to the spi message
1709 struct stm32_spi *spi = spi_master_get_devdata(master);
1711 spi->cfg->disable(spi);
1718 * @spi: pointer to the spi controller data structure
1720 static int stm32f4_spi_config(struct stm32_spi *spi)
1724 spin_lock_irqsave(&spi->lock, flags);
1727 stm32_spi_clr_bits(spi, STM32F4_SPI_I2SCFGR,
1737 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SSI |
1742 spin_unlock_irqrestore(&spi->lock, flags);
1749 * @spi: pointer to the spi controller data structure
1751 static int stm32h7_spi_config(struct stm32_spi *spi)
1755 spin_lock_irqsave(&spi->lock, flags);
1758 stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR,
1766 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SSI |
1776 stm32_spi_set_bits(spi, STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_MASTER |
1780 spin_unlock_irqrestore(&spi->lock, flags);
1824 { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg },
1825 { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg },
1833 struct stm32_spi *spi;
1839 dev_err(&pdev->dev, "spi master allocation failed\n");
1844 spi = spi_master_get_devdata(master);
1845 spi->dev = &pdev->dev;
1846 spi->master = master;
1847 spin_lock_init(&spi->lock);
1849 spi->cfg = (const struct stm32_spi_cfg *)
1854 spi->base = devm_ioremap_resource(&pdev->dev, res);
1855 if (IS_ERR(spi->base))
1856 return PTR_ERR(spi->base);
1858 spi->phys_addr = (dma_addr_t)res->start;
1860 spi->irq = platform_get_irq(pdev, 0);
1861 if (spi->irq <= 0)
1862 return dev_err_probe(&pdev->dev, spi->irq,
1865 ret = devm_request_threaded_irq(&pdev->dev, spi->irq,
1866 spi->cfg->irq_handler_event,
1867 spi->cfg->irq_handler_thread,
1870 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq,
1875 spi->clk = devm_clk_get(&pdev->dev, NULL);
1876 if (IS_ERR(spi->clk)) {
1877 ret = PTR_ERR(spi->clk);
1882 ret = clk_prepare_enable(spi->clk);
1887 spi->clk_rate = clk_get_rate(spi->clk);
1888 if (!spi->clk_rate) {
1894 spi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1895 if (!IS_ERR(spi->rst)) {
1896 reset_control_assert(spi->rst);
1898 reset_control_deassert(spi->rst);
1901 if (spi->cfg->has_fifo)
1902 spi->fifo_size = spi->cfg->get_fifo_size(spi);
1904 ret = spi->cfg->config(spi);
1916 master->bits_per_word_mask = spi->cfg->get_bpw_mask(spi);
1917 master->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min;
1918 master->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max;
1925 spi->dma_tx = dma_request_chan(spi->dev, "tx");
1926 if (IS_ERR(spi->dma_tx)) {
1927 ret = PTR_ERR(spi->dma_tx);
1928 spi->dma_tx = NULL;
1934 master->dma_tx = spi->dma_tx;
1937 spi->dma_rx = dma_request_chan(spi->dev, "rx");
1938 if (IS_ERR(spi->dma_rx)) {
1939 ret = PTR_ERR(spi->dma_rx);
1940 spi->dma_rx = NULL;
1946 master->dma_rx = spi->dma_rx;
1949 if (spi->dma_tx || spi->dma_rx)
1958 dev_err(&pdev->dev, "spi master registration failed: %d\n",
1978 if (spi->dma_tx)
1979 dma_release_channel(spi->dma_tx);
1980 if (spi->dma_rx)
1981 dma_release_channel(spi->dma_rx);
1983 clk_disable_unprepare(spi->clk);
1991 struct stm32_spi *spi = spi_master_get_devdata(master);
1996 spi->cfg->disable(spi);
2006 clk_disable_unprepare(spi->clk);
2018 struct stm32_spi *spi = spi_master_get_devdata(master);
2020 clk_disable_unprepare(spi->clk);
2028 struct stm32_spi *spi = spi_master_get_devdata(master);
2035 return clk_prepare_enable(spi->clk);
2055 struct stm32_spi *spi = spi_master_get_devdata(master);
2064 clk_disable_unprepare(spi->clk);
2075 spi->cfg->config(spi);