Lines Matching refs:val
196 u32 val, us;
200 ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_INT_RAW_STS, val,
201 val & SPRD_SPI_TX_END_IRQ, 0, us);
207 ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_STS2, val,
208 !(val & SPRD_SPI_TX_BUSY), 0, us);
221 u32 val, us;
225 ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_INT_RAW_STS, val,
226 val & SPRD_SPI_RX_END_IRQ, 0, us);
249 u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL1);
251 val &= ~SPRD_SPI_RTX_MD_MASK;
252 writel_relaxed(val, ss->base + SPRD_SPI_CTL1);
257 u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL0);
260 val &= ~(SPRD_SPI_CHNL_LEN_MASK << SPRD_SPI_CHNL_LEN);
261 val |= bits << SPRD_SPI_CHNL_LEN;
262 writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
267 u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL8);
270 val &= ~SPRD_SPI_TX_LEN_H_MASK;
271 val |= length >> SPRD_SPI_TX_LEN_H_OFFSET;
272 writel_relaxed(val, ss->base + SPRD_SPI_CTL8);
274 val = length & SPRD_SPI_TX_LEN_L_MASK;
275 writel_relaxed(val, ss->base + SPRD_SPI_CTL9);
280 u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL10);
283 val &= ~SPRD_SPI_RX_LEN_H_MASK;
284 val |= length >> SPRD_SPI_RX_LEN_H_OFFSET;
285 writel_relaxed(val, ss->base + SPRD_SPI_CTL10);
287 val = length & SPRD_SPI_RX_LEN_L_MASK;
288 writel_relaxed(val, ss->base + SPRD_SPI_CTL11);
295 u32 val;
297 val = readl_relaxed(ss->base + SPRD_SPI_CTL0);
300 val &= ~SPRD_SPI_CS0_VALID;
301 writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
303 val |= SPRD_SPI_CSN_MASK;
304 writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
310 u32 val;
313 val = readl_relaxed(ss->base + SPRD_SPI_CTL4);
314 val &= ~(SPRD_SPI_START_RX | SPRD_SPI_ONLY_RECV_MASK);
315 writel_relaxed(val, ss->base + SPRD_SPI_CTL4);
318 val = readl_relaxed(ss->base + SPRD_SPI_CTL4);
319 val |= len & SPRD_SPI_ONLY_RECV_MASK;
320 writel_relaxed(val, ss->base + SPRD_SPI_CTL4);
323 val = readl_relaxed(ss->base + SPRD_SPI_CTL4);
324 val |= SPRD_SPI_START_RX;
325 writel_relaxed(val, ss->base + SPRD_SPI_CTL4);
459 u32 val;
465 val = readl_relaxed(ss->base + SPRD_SPI_INT_EN);
466 writel_relaxed(val | SPRD_SPI_TX_END_INT_EN |
478 u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL2);
481 val |= SPRD_SPI_DMA_EN;
483 val &= ~SPRD_SPI_DMA_EN;
485 writel_relaxed(val, ss->base + SPRD_SPI_CTL2);
669 u32 val;
674 val = readl_relaxed(ss->base + SPRD_SPI_CTL0);
675 val &= ~(SPRD_SPI_SCK_REV | SPRD_SPI_NG_TX | SPRD_SPI_NG_RX);
677 val |= ss->hw_mode & SPI_CPHA ? SPRD_SPI_NG_RX : SPRD_SPI_NG_TX;
678 val |= ss->hw_mode & SPI_CPOL ? SPRD_SPI_SCK_REV : 0;
679 writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
697 val = readl_relaxed(ss->base + SPRD_SPI_CTL7);
698 val &= ~SPRD_SPI_MODE_MASK;
701 val |= SPRD_SPI_3WIRE_MODE << SPRD_SPI_MODE_OFFSET;
703 val |= SPRD_SPI_4WIRE_MODE << SPRD_SPI_MODE_OFFSET;
706 val |= SPRD_SPI_DATA_LINE2_EN;
708 val &= ~SPRD_SPI_DATA_LINE2_EN;
710 writel_relaxed(val, ss->base + SPRD_SPI_CTL7);
720 u32 val, mode = 0;
768 val = readl_relaxed(ss->base + SPRD_SPI_CTL1);
769 val &= ~SPRD_SPI_RTX_MD_MASK;
775 writel_relaxed(val | mode, ss->base + SPRD_SPI_CTL1);
818 u32 val = readl_relaxed(ss->base + SPRD_SPI_INT_MASK_STS);
820 if (val & SPRD_SPI_MASK_TX_END) {
828 if (val & SPRD_SPI_MASK_RX_END) {