Lines Matching refs:ss
169 int (*read_bufs)(struct sprd_spi *ss, u32 len);
170 int (*write_bufs)(struct sprd_spi *ss, u32 len);
173 static u32 sprd_spi_transfer_max_timeout(struct sprd_spi *ss,
181 u32 bit_time_us = DIV_ROUND_UP(USEC_PER_SEC, ss->hw_speed_hz);
187 u32 interval_cycle = SPRD_SPI_FIFO_SIZE * ss->word_delay;
189 ss->src_clk);
194 static int sprd_spi_wait_for_tx_end(struct sprd_spi *ss, struct spi_transfer *t)
199 us = sprd_spi_transfer_max_timeout(ss, t);
200 ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_INT_RAW_STS, val,
203 dev_err(ss->dev, "SPI error, spi send timeout!\n");
207 ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_STS2, val,
210 dev_err(ss->dev, "SPI error, spi busy timeout!\n");
214 writel_relaxed(SPRD_SPI_TX_END_INT_CLR, ss->base + SPRD_SPI_INT_CLR);
219 static int sprd_spi_wait_for_rx_end(struct sprd_spi *ss, struct spi_transfer *t)
224 us = sprd_spi_transfer_max_timeout(ss, t);
225 ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_INT_RAW_STS, val,
228 dev_err(ss->dev, "SPI error, spi rx timeout!\n");
232 writel_relaxed(SPRD_SPI_RX_END_INT_CLR, ss->base + SPRD_SPI_INT_CLR);
237 static void sprd_spi_tx_req(struct sprd_spi *ss)
239 writel_relaxed(SPRD_SPI_SW_TX_REQ, ss->base + SPRD_SPI_CTL12);
242 static void sprd_spi_rx_req(struct sprd_spi *ss)
244 writel_relaxed(SPRD_SPI_SW_RX_REQ, ss->base + SPRD_SPI_CTL12);
247 static void sprd_spi_enter_idle(struct sprd_spi *ss)
249 u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL1);
252 writel_relaxed(val, ss->base + SPRD_SPI_CTL1);
255 static void sprd_spi_set_transfer_bits(struct sprd_spi *ss, u32 bits)
257 u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL0);
262 writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
265 static void sprd_spi_set_tx_length(struct sprd_spi *ss, u32 length)
267 u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL8);
272 writel_relaxed(val, ss->base + SPRD_SPI_CTL8);
275 writel_relaxed(val, ss->base + SPRD_SPI_CTL9);
278 static void sprd_spi_set_rx_length(struct sprd_spi *ss, u32 length)
280 u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL10);
285 writel_relaxed(val, ss->base + SPRD_SPI_CTL10);
288 writel_relaxed(val, ss->base + SPRD_SPI_CTL11);
294 struct sprd_spi *ss = spi_controller_get_devdata(sctlr);
297 val = readl_relaxed(ss->base + SPRD_SPI_CTL0);
301 writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
304 writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
308 static int sprd_spi_write_only_receive(struct sprd_spi *ss, u32 len)
313 val = readl_relaxed(ss->base + SPRD_SPI_CTL4);
315 writel_relaxed(val, ss->base + SPRD_SPI_CTL4);
318 val = readl_relaxed(ss->base + SPRD_SPI_CTL4);
320 writel_relaxed(val, ss->base + SPRD_SPI_CTL4);
323 val = readl_relaxed(ss->base + SPRD_SPI_CTL4);
325 writel_relaxed(val, ss->base + SPRD_SPI_CTL4);
330 static int sprd_spi_write_bufs_u8(struct sprd_spi *ss, u32 len)
332 u8 *tx_p = (u8 *)ss->tx_buf;
336 writeb_relaxed(tx_p[i], ss->base + SPRD_SPI_TXD);
338 ss->tx_buf += i;
342 static int sprd_spi_write_bufs_u16(struct sprd_spi *ss, u32 len)
344 u16 *tx_p = (u16 *)ss->tx_buf;
348 writew_relaxed(tx_p[i], ss->base + SPRD_SPI_TXD);
350 ss->tx_buf += i << 1;
354 static int sprd_spi_write_bufs_u32(struct sprd_spi *ss, u32 len)
356 u32 *tx_p = (u32 *)ss->tx_buf;
360 writel_relaxed(tx_p[i], ss->base + SPRD_SPI_TXD);
362 ss->tx_buf += i << 2;
366 static int sprd_spi_read_bufs_u8(struct sprd_spi *ss, u32 len)
368 u8 *rx_p = (u8 *)ss->rx_buf;
372 rx_p[i] = readb_relaxed(ss->base + SPRD_SPI_TXD);
374 ss->rx_buf += i;
378 static int sprd_spi_read_bufs_u16(struct sprd_spi *ss, u32 len)
380 u16 *rx_p = (u16 *)ss->rx_buf;
384 rx_p[i] = readw_relaxed(ss->base + SPRD_SPI_TXD);
386 ss->rx_buf += i << 1;
390 static int sprd_spi_read_bufs_u32(struct sprd_spi *ss, u32 len)
392 u32 *rx_p = (u32 *)ss->rx_buf;
396 rx_p[i] = readl_relaxed(ss->base + SPRD_SPI_TXD);
398 ss->rx_buf += i << 2;
404 struct sprd_spi *ss = spi_controller_get_devdata(sdev->controller);
405 u32 trans_len = ss->trans_len, len;
411 if (ss->trans_mode & SPRD_SPI_TX_MODE) {
412 sprd_spi_set_tx_length(ss, len);
413 write_size += ss->write_bufs(ss, len);
419 if (ss->hw_mode & SPI_3WIRE || ss->hw_mode & SPI_TX_DUAL)
420 sprd_spi_tx_req(ss);
422 ret = sprd_spi_wait_for_tx_end(ss, t);
424 sprd_spi_set_rx_length(ss, len);
430 if (ss->hw_mode & SPI_3WIRE || ss->hw_mode & SPI_TX_DUAL)
431 sprd_spi_rx_req(ss);
433 write_size += ss->write_bufs(ss, len);
435 ret = sprd_spi_wait_for_rx_end(ss, t);
441 if (ss->trans_mode & SPRD_SPI_RX_MODE)
442 read_size += ss->read_bufs(ss, len);
447 if (ss->trans_mode & SPRD_SPI_TX_MODE)
452 sprd_spi_enter_idle(ss);
457 static void sprd_spi_irq_enable(struct sprd_spi *ss)
463 ss->base + SPRD_SPI_INT_CLR);
465 val = readl_relaxed(ss->base + SPRD_SPI_INT_EN);
468 ss->base + SPRD_SPI_INT_EN);
471 static void sprd_spi_irq_disable(struct sprd_spi *ss)
473 writel_relaxed(0, ss->base + SPRD_SPI_INT_EN);
476 static void sprd_spi_dma_enable(struct sprd_spi *ss, bool enable)
478 u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL2);
485 writel_relaxed(val, ss->base + SPRD_SPI_CTL2);
517 static int sprd_spi_dma_rx_config(struct sprd_spi *ss, struct spi_transfer *t)
519 struct dma_chan *dma_chan = ss->dma.dma_chan[SPRD_SPI_RX];
521 .src_addr = ss->phy_base,
522 .src_addr_width = ss->dma.width,
523 .dst_addr_width = ss->dma.width,
524 .dst_maxburst = ss->dma.fragmens_len,
532 return ss->dma.rx_len;
535 static int sprd_spi_dma_tx_config(struct sprd_spi *ss, struct spi_transfer *t)
537 struct dma_chan *dma_chan = ss->dma.dma_chan[SPRD_SPI_TX];
539 .dst_addr = ss->phy_base,
540 .src_addr_width = ss->dma.width,
541 .dst_addr_width = ss->dma.width,
542 .src_maxburst = ss->dma.fragmens_len,
553 static int sprd_spi_dma_request(struct sprd_spi *ss)
555 ss->dma.dma_chan[SPRD_SPI_RX] = dma_request_chan(ss->dev, "rx_chn");
556 if (IS_ERR_OR_NULL(ss->dma.dma_chan[SPRD_SPI_RX]))
557 return dev_err_probe(ss->dev, PTR_ERR(ss->dma.dma_chan[SPRD_SPI_RX]),
560 ss->dma.dma_chan[SPRD_SPI_TX] = dma_request_chan(ss->dev, "tx_chn");
561 if (IS_ERR_OR_NULL(ss->dma.dma_chan[SPRD_SPI_TX])) {
562 dma_release_channel(ss->dma.dma_chan[SPRD_SPI_RX]);
563 return dev_err_probe(ss->dev, PTR_ERR(ss->dma.dma_chan[SPRD_SPI_TX]),
570 static void sprd_spi_dma_release(struct sprd_spi *ss)
572 if (ss->dma.dma_chan[SPRD_SPI_RX])
573 dma_release_channel(ss->dma.dma_chan[SPRD_SPI_RX]);
575 if (ss->dma.dma_chan[SPRD_SPI_TX])
576 dma_release_channel(ss->dma.dma_chan[SPRD_SPI_TX]);
582 struct sprd_spi *ss = spi_master_get_devdata(sdev->master);
583 u32 trans_len = ss->trans_len;
586 reinit_completion(&ss->xfer_completion);
587 sprd_spi_irq_enable(ss);
588 if (ss->trans_mode & SPRD_SPI_TX_MODE) {
589 write_size = sprd_spi_dma_tx_config(ss, t);
590 sprd_spi_set_tx_length(ss, trans_len);
596 if (ss->hw_mode & SPI_3WIRE || ss->hw_mode & SPI_TX_DUAL)
597 sprd_spi_tx_req(ss);
599 sprd_spi_set_rx_length(ss, trans_len);
605 if (ss->hw_mode & SPI_3WIRE || ss->hw_mode & SPI_TX_DUAL)
606 sprd_spi_rx_req(ss);
608 write_size = ss->write_bufs(ss, trans_len);
613 dev_err(ss->dev, "failed to write, ret = %d\n", ret);
617 if (ss->trans_mode & SPRD_SPI_RX_MODE) {
625 ss->dma.rx_len = t->len > ss->dma.fragmens_len ?
626 (t->len - t->len % ss->dma.fragmens_len) :
628 ret = sprd_spi_dma_rx_config(ss, t);
636 sprd_spi_dma_enable(ss, true);
637 wait_for_completion(&(ss->xfer_completion));
639 if (ss->trans_mode & SPRD_SPI_TX_MODE)
642 ret = ss->dma.rx_len;
645 sprd_spi_dma_enable(ss, false);
646 sprd_spi_enter_idle(ss);
647 sprd_spi_irq_disable(ss);
652 static void sprd_spi_set_speed(struct sprd_spi *ss, u32 speed_hz)
658 u32 clk_div = DIV_ROUND_UP(ss->src_clk, speed_hz << 1) - 1;
661 ss->hw_speed_hz = (ss->src_clk >> 1) / (clk_div + 1);
662 writel_relaxed(clk_div, ss->base + SPRD_SPI_CLKD);
665 static int sprd_spi_init_hw(struct sprd_spi *ss, struct spi_transfer *t)
674 val = readl_relaxed(ss->base + SPRD_SPI_CTL0);
677 val |= ss->hw_mode & SPI_CPHA ? SPRD_SPI_NG_RX : SPRD_SPI_NG_TX;
678 val |= ss->hw_mode & SPI_CPOL ? SPRD_SPI_SCK_REV : 0;
679 writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
689 ss->word_delay = interval * 4 + 10;
690 writel_relaxed(interval, ss->base + SPRD_SPI_CTL5);
693 writel_relaxed(1, ss->base + SPRD_SPI_FIFO_RST);
694 writel_relaxed(0, ss->base + SPRD_SPI_FIFO_RST);
697 val = readl_relaxed(ss->base + SPRD_SPI_CTL7);
700 if (ss->hw_mode & SPI_3WIRE)
705 if (ss->hw_mode & SPI_TX_DUAL)
710 writel_relaxed(val, ss->base + SPRD_SPI_CTL7);
718 struct sprd_spi *ss = spi_controller_get_devdata(sdev->controller);
723 ss->len = t->len;
724 ss->tx_buf = t->tx_buf;
725 ss->rx_buf = t->rx_buf;
727 ss->hw_mode = sdev->mode;
728 ret = sprd_spi_init_hw(ss, t);
733 sprd_spi_set_speed(ss, t->speed_hz);
734 sprd_spi_set_transfer_bits(ss, bits_per_word);
743 ss->trans_len = t->len;
744 ss->read_bufs = sprd_spi_read_bufs_u8;
745 ss->write_bufs = sprd_spi_write_bufs_u8;
746 ss->dma.width = DMA_SLAVE_BUSWIDTH_1_BYTE;
747 ss->dma.fragmens_len = SPRD_SPI_DMA_STEP;
750 ss->trans_len = t->len >> 1;
751 ss->read_bufs = sprd_spi_read_bufs_u16;
752 ss->write_bufs = sprd_spi_write_bufs_u16;
753 ss->dma.width = DMA_SLAVE_BUSWIDTH_2_BYTES;
754 ss->dma.fragmens_len = SPRD_SPI_DMA_STEP << 1;
757 ss->trans_len = t->len >> 2;
758 ss->read_bufs = sprd_spi_read_bufs_u32;
759 ss->write_bufs = sprd_spi_write_bufs_u32;
760 ss->dma.width = DMA_SLAVE_BUSWIDTH_4_BYTES;
761 ss->dma.fragmens_len = SPRD_SPI_DMA_STEP << 2;
768 val = readl_relaxed(ss->base + SPRD_SPI_CTL1);
775 writel_relaxed(val | mode, ss->base + SPRD_SPI_CTL1);
777 ss->trans_mode = mode;
783 if (ss->trans_mode == SPRD_SPI_RX_MODE)
784 ss->write_bufs = sprd_spi_write_only_receive;
817 struct sprd_spi *ss = (struct sprd_spi *)data;
818 u32 val = readl_relaxed(ss->base + SPRD_SPI_INT_MASK_STS);
821 writel_relaxed(SPRD_SPI_TX_END_CLR, ss->base + SPRD_SPI_INT_CLR);
822 if (!(ss->trans_mode & SPRD_SPI_RX_MODE))
823 complete(&ss->xfer_completion);
829 writel_relaxed(SPRD_SPI_RX_END_CLR, ss->base + SPRD_SPI_INT_CLR);
830 if (ss->dma.rx_len < ss->len) {
831 ss->rx_buf += ss->dma.rx_len;
832 ss->dma.rx_len +=
833 ss->read_bufs(ss, ss->len - ss->dma.rx_len);
835 complete(&ss->xfer_completion);
843 static int sprd_spi_irq_init(struct platform_device *pdev, struct sprd_spi *ss)
847 ss->irq = platform_get_irq(pdev, 0);
848 if (ss->irq < 0)
849 return ss->irq;
851 ret = devm_request_irq(&pdev->dev, ss->irq, sprd_spi_handle_irq,
852 0, pdev->name, ss);
855 ss->irq, ret);
860 static int sprd_spi_clk_init(struct platform_device *pdev, struct sprd_spi *ss)
876 ss->clk = devm_clk_get(&pdev->dev, "enable");
877 if (IS_ERR(ss->clk)) {
879 return PTR_ERR(ss->clk);
883 ss->src_clk = clk_get_rate(clk_spi);
885 ss->src_clk = SPRD_SPI_DEFAULT_SOURCE;
893 struct sprd_spi *ss = spi_controller_get_devdata(sctlr);
895 return ss->dma.enable && (t->len > SPRD_SPI_FIFO_SIZE);
898 static int sprd_spi_dma_init(struct platform_device *pdev, struct sprd_spi *ss)
902 ret = sprd_spi_dma_request(ss);
914 ss->dma.enable = true;
923 struct sprd_spi *ss;
927 sctlr = spi_alloc_master(&pdev->dev, sizeof(*ss));
931 ss = spi_controller_get_devdata(sctlr);
933 ss->base = devm_ioremap_resource(&pdev->dev, res);
934 if (IS_ERR(ss->base)) {
935 ret = PTR_ERR(ss->base);
939 ss->phy_base = res->start;
940 ss->dev = &pdev->dev;
948 sctlr->max_speed_hz = min_t(u32, ss->src_clk >> 1,
951 init_completion(&ss->xfer_completion);
953 ret = sprd_spi_clk_init(pdev, ss);
957 ret = sprd_spi_irq_init(pdev, ss);
961 ret = sprd_spi_dma_init(pdev, ss);
965 ret = clk_prepare_enable(ss->clk);
996 clk_disable_unprepare(ss->clk);
998 sprd_spi_dma_release(ss);
1008 struct sprd_spi *ss = spi_controller_get_devdata(sctlr);
1011 ret = pm_runtime_get_sync(ss->dev);
1013 pm_runtime_put_noidle(ss->dev);
1014 dev_err(ss->dev, "failed to resume SPI controller\n");
1020 if (ss->dma.enable)
1021 sprd_spi_dma_release(ss);
1022 clk_disable_unprepare(ss->clk);
1032 struct sprd_spi *ss = spi_controller_get_devdata(sctlr);
1034 if (ss->dma.enable)
1035 sprd_spi_dma_release(ss);
1037 clk_disable_unprepare(ss->clk);
1045 struct sprd_spi *ss = spi_controller_get_devdata(sctlr);
1048 ret = clk_prepare_enable(ss->clk);
1052 if (!ss->dma.enable)
1055 ret = sprd_spi_dma_request(ss);
1057 clk_disable_unprepare(ss->clk);