Lines Matching defs:sspi
300 void (*hwinit)(struct sirfsoc_spi *sspi);
303 static void sirfsoc_usp_hwinit(struct sirfsoc_spi *sspi)
306 writel(readl(sspi->base + sspi->regs->usp_mode1) &
307 ~SIRFSOC_USP_EN, sspi->base + sspi->regs->usp_mode1);
308 writel(readl(sspi->base + sspi->regs->usp_mode1) |
309 SIRFSOC_USP_EN, sspi->base + sspi->regs->usp_mode1);
312 static void spi_sirfsoc_rx_word_u8(struct sirfsoc_spi *sspi)
315 u8 *rx = sspi->rx;
317 data = readl(sspi->base + sspi->regs->rxfifo_data);
321 sspi->rx = rx;
324 sspi->left_rx_word--;
327 static void spi_sirfsoc_tx_word_u8(struct sirfsoc_spi *sspi)
330 const u8 *tx = sspi->tx;
334 sspi->tx = tx;
336 writel(data, sspi->base + sspi->regs->txfifo_data);
337 sspi->left_tx_word--;
340 static void spi_sirfsoc_rx_word_u16(struct sirfsoc_spi *sspi)
343 u16 *rx = sspi->rx;
345 data = readl(sspi->base + sspi->regs->rxfifo_data);
349 sspi->rx = rx;
352 sspi->left_rx_word--;
355 static void spi_sirfsoc_tx_word_u16(struct sirfsoc_spi *sspi)
358 const u16 *tx = sspi->tx;
362 sspi->tx = tx;
365 writel(data, sspi->base + sspi->regs->txfifo_data);
366 sspi->left_tx_word--;
369 static void spi_sirfsoc_rx_word_u32(struct sirfsoc_spi *sspi)
372 u32 *rx = sspi->rx;
374 data = readl(sspi->base + sspi->regs->rxfifo_data);
378 sspi->rx = rx;
381 sspi->left_rx_word--;
385 static void spi_sirfsoc_tx_word_u32(struct sirfsoc_spi *sspi)
388 const u32 *tx = sspi->tx;
392 sspi->tx = tx;
395 writel(data, sspi->base + sspi->regs->txfifo_data);
396 sspi->left_tx_word--;
401 struct sirfsoc_spi *sspi = dev_id;
404 spi_stat = readl(sspi->base + sspi->regs->int_st);
405 if (sspi->tx_by_cmd && sspi->type == SIRF_REAL_SPI
407 complete(&sspi->tx_done);
408 writel(0x0, sspi->base + sspi->regs->int_en);
409 writel(readl(sspi->base + sspi->regs->int_st),
410 sspi->base + sspi->regs->int_st);
416 complete(&sspi->tx_done);
417 complete(&sspi->rx_done);
418 switch (sspi->type) {
421 writel(0x0, sspi->base + sspi->regs->int_en);
424 writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr);
427 writel(readl(sspi->base + sspi->regs->int_st),
428 sspi->base + sspi->regs->int_st);
432 complete(&sspi->tx_done);
433 while (!(readl(sspi->base + sspi->regs->int_st) &
436 complete(&sspi->rx_done);
437 switch (sspi->type) {
440 writel(0x0, sspi->base + sspi->regs->int_en);
443 writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr);
446 writel(readl(sspi->base + sspi->regs->int_st),
447 sspi->base + sspi->regs->int_st);
462 struct sirfsoc_spi *sspi;
466 sspi = spi_master_get_devdata(spi->master);
467 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op);
468 writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->txfifo_op);
469 memcpy(&cmd, sspi->tx, t->len);
470 if (sspi->word_width == 1 && !(spi->mode & SPI_LSB_FIRST))
473 if (sspi->word_width == 2 && t->len == 4 &&
476 writel(cmd, sspi->base + sspi->regs->spi_cmd);
478 sspi->base + sspi->regs->int_en);
480 sspi->base + sspi->regs->tx_rx_en);
481 if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
485 sspi->left_rx_word -= t->len;
491 struct sirfsoc_spi *sspi;
495 sspi = spi_master_get_devdata(spi->master);
496 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->rxfifo_op);
497 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op);
498 switch (sspi->type) {
501 sspi->base + sspi->regs->rxfifo_op);
503 sspi->base + sspi->regs->txfifo_op);
504 writel(0, sspi->base + sspi->regs->int_en);
507 writel(0x0, sspi->base + sspi->regs->rxfifo_op);
508 writel(0x0, sspi->base + sspi->regs->txfifo_op);
509 writel(0, sspi->base + sspi->regs->int_en);
512 writel(0x0, sspi->base + sspi->regs->rxfifo_op);
513 writel(0x0, sspi->base + sspi->regs->txfifo_op);
514 writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr);
517 writel(readl(sspi->base + sspi->regs->int_st),
518 sspi->base + sspi->regs->int_st);
519 if (sspi->left_tx_word < sspi->dat_max_frm_len) {
520 switch (sspi->type) {
522 writel(readl(sspi->base + sspi->regs->spi_ctrl) |
525 sspi->base + sspi->regs->spi_ctrl);
526 writel(sspi->left_tx_word - 1,
527 sspi->base + sspi->regs->tx_dma_io_len);
528 writel(sspi->left_tx_word - 1,
529 sspi->base + sspi->regs->rx_dma_io_len);
534 writel(sspi->left_tx_word * sspi->word_width,
535 sspi->base + sspi->regs->tx_dma_io_len);
536 writel(sspi->left_tx_word * sspi->word_width,
537 sspi->base + sspi->regs->rx_dma_io_len);
541 if (sspi->type == SIRF_REAL_SPI)
542 writel(readl(sspi->base + sspi->regs->spi_ctrl),
543 sspi->base + sspi->regs->spi_ctrl);
544 writel(0, sspi->base + sspi->regs->tx_dma_io_len);
545 writel(0, sspi->base + sspi->regs->rx_dma_io_len);
547 sspi->dst_start = dma_map_single(&spi->dev, sspi->rx, t->len,
550 rx_desc = dmaengine_prep_slave_single(sspi->rx_chan,
551 sspi->dst_start, t->len, DMA_DEV_TO_MEM,
554 rx_desc->callback_param = &sspi->rx_done;
556 sspi->src_start = dma_map_single(&spi->dev, (void *)sspi->tx, t->len,
559 tx_desc = dmaengine_prep_slave_single(sspi->tx_chan,
560 sspi->src_start, t->len, DMA_MEM_TO_DEV,
563 tx_desc->callback_param = &sspi->tx_done;
567 dma_async_issue_pending(sspi->tx_chan);
568 dma_async_issue_pending(sspi->rx_chan);
570 sspi->base + sspi->regs->tx_rx_en);
571 if (sspi->type == SIRF_USP_SPI_P2 ||
572 sspi->type == SIRF_USP_SPI_A7) {
574 sspi->base + sspi->regs->rxfifo_op);
576 sspi->base + sspi->regs->txfifo_op);
578 if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0) {
580 dmaengine_terminate_all(sspi->rx_chan);
582 sspi->left_rx_word = 0;
588 if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
590 if (sspi->type == SIRF_USP_SPI_P2 ||
591 sspi->type == SIRF_USP_SPI_A7)
592 writel(0, sspi->base + sspi->regs->tx_rx_en);
593 dmaengine_terminate_all(sspi->tx_chan);
595 dma_unmap_single(&spi->dev, sspi->src_start, t->len, DMA_TO_DEVICE);
596 dma_unmap_single(&spi->dev, sspi->dst_start, t->len, DMA_FROM_DEVICE);
598 writel(0, sspi->base + sspi->regs->rxfifo_op);
599 writel(0, sspi->base + sspi->regs->txfifo_op);
600 if (sspi->left_tx_word >= sspi->dat_max_frm_len)
601 writel(0, sspi->base + sspi->regs->tx_rx_en);
602 if (sspi->type == SIRF_USP_SPI_P2 ||
603 sspi->type == SIRF_USP_SPI_A7)
604 writel(0, sspi->base + sspi->regs->tx_rx_en);
610 struct sirfsoc_spi *sspi;
614 sspi = spi_master_get_devdata(spi->master);
617 sspi->base + sspi->regs->rxfifo_op);
619 sspi->base + sspi->regs->txfifo_op);
620 switch (sspi->type) {
622 writel(0x0, sspi->base + sspi->regs->rxfifo_op);
623 writel(0x0, sspi->base + sspi->regs->txfifo_op);
624 writel(0, sspi->base + sspi->regs->int_en);
625 writel(readl(sspi->base + sspi->regs->int_st),
626 sspi->base + sspi->regs->int_st);
627 writel(min((sspi->left_tx_word * sspi->word_width),
628 sspi->fifo_size),
629 sspi->base + sspi->regs->tx_dma_io_len);
630 writel(min((sspi->left_rx_word * sspi->word_width),
631 sspi->fifo_size),
632 sspi->base + sspi->regs->rx_dma_io_len);
635 writel(0x0, sspi->base + sspi->regs->rxfifo_op);
636 writel(0x0, sspi->base + sspi->regs->txfifo_op);
637 writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr);
638 writel(readl(sspi->base + sspi->regs->int_st),
639 sspi->base + sspi->regs->int_st);
640 writel(min((sspi->left_tx_word * sspi->word_width),
641 sspi->fifo_size),
642 sspi->base + sspi->regs->tx_dma_io_len);
643 writel(min((sspi->left_rx_word * sspi->word_width),
644 sspi->fifo_size),
645 sspi->base + sspi->regs->rx_dma_io_len);
649 sspi->base + sspi->regs->rxfifo_op);
651 sspi->base + sspi->regs->txfifo_op);
652 writel(0, sspi->base + sspi->regs->int_en);
653 writel(readl(sspi->base + sspi->regs->int_st),
654 sspi->base + sspi->regs->int_st);
655 writel(readl(sspi->base + sspi->regs->spi_ctrl) |
658 sspi->base + sspi->regs->spi_ctrl);
659 data_units = sspi->fifo_size / sspi->word_width;
660 writel(min(sspi->left_tx_word, data_units) - 1,
661 sspi->base + sspi->regs->tx_dma_io_len);
662 writel(min(sspi->left_rx_word, data_units) - 1,
663 sspi->base + sspi->regs->rx_dma_io_len);
666 while (!((readl(sspi->base + sspi->regs->txfifo_st)
667 & SIRFSOC_SPI_FIFO_FULL_MASK(sspi))) &&
668 sspi->left_tx_word)
669 sspi->tx_word(sspi);
674 sspi->base + sspi->regs->int_en);
676 sspi->base + sspi->regs->tx_rx_en);
677 if (sspi->type == SIRF_USP_SPI_P2 ||
678 sspi->type == SIRF_USP_SPI_A7) {
680 sspi->base + sspi->regs->rxfifo_op);
682 sspi->base + sspi->regs->txfifo_op);
684 if (!wait_for_completion_timeout(&sspi->tx_done, timeout) ||
685 !wait_for_completion_timeout(&sspi->rx_done, timeout)) {
687 if (sspi->type == SIRF_USP_SPI_P2 ||
688 sspi->type == SIRF_USP_SPI_A7)
689 writel(0, sspi->base + sspi->regs->tx_rx_en);
692 while (!((readl(sspi->base + sspi->regs->rxfifo_st)
693 & SIRFSOC_SPI_FIFO_EMPTY_MASK(sspi))) &&
694 sspi->left_rx_word)
695 sspi->rx_word(sspi);
696 if (sspi->type == SIRF_USP_SPI_P2 ||
697 sspi->type == SIRF_USP_SPI_A7)
698 writel(0, sspi->base + sspi->regs->tx_rx_en);
699 writel(0, sspi->base + sspi->regs->rxfifo_op);
700 writel(0, sspi->base + sspi->regs->txfifo_op);
701 } while (sspi->left_tx_word != 0 || sspi->left_rx_word != 0);
706 struct sirfsoc_spi *sspi;
708 sspi = spi_master_get_devdata(spi->master);
709 sspi->tx = t->tx_buf;
710 sspi->rx = t->rx_buf;
711 sspi->left_tx_word = sspi->left_rx_word = t->len / sspi->word_width;
712 reinit_completion(&sspi->rx_done);
713 reinit_completion(&sspi->tx_done);
719 if (sspi->type == SIRF_REAL_SPI && sspi->tx_by_cmd)
726 return t->len - sspi->left_rx_word * sspi->word_width;
731 struct sirfsoc_spi *sspi = spi_master_get_devdata(spi->master);
733 if (sspi->hw_cs) {
736 switch (sspi->type) {
738 regval = readl(sspi->base + sspi->regs->spi_ctrl);
753 writel(regval, sspi->base + sspi->regs->spi_ctrl);
757 regval = readl(sspi->base +
758 sspi->regs->usp_pin_io_data);
774 sspi->base + sspi->regs->usp_pin_io_data);
793 struct sirfsoc_spi *sspi;
796 sspi = spi_master_get_devdata(spi->master);
797 regval = readl(sspi->base + sspi->regs->spi_ctrl);
798 usp_mode1 = readl(sspi->base + sspi->regs->usp_mode1);
834 writel((SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size - 2) <<
836 (SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size / 2) <<
838 (SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, 2) <<
840 sspi->base + sspi->regs->txfifo_level_chk);
841 writel((SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, 2) <<
843 (SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size / 2) <<
845 (SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size - 2) <<
847 sspi->base + sspi->regs->rxfifo_level_chk);
852 switch (sspi->type) {
855 writel(regval, sspi->base + sspi->regs->spi_ctrl);
862 writel(usp_mode1, sspi->base + sspi->regs->usp_mode1);
872 struct sirfsoc_spi *sspi;
877 sspi = spi_master_get_devdata(spi->master);
882 usp_mode2 = regval = (sspi->ctrl_freq / (2 * hz)) - 1;
890 sspi->rx_word = spi_sirfsoc_rx_word_u8;
891 sspi->tx_word = spi_sirfsoc_tx_word_u8;
898 sspi->rx_word = spi_sirfsoc_rx_word_u16;
899 sspi->tx_word = spi_sirfsoc_tx_word_u16;
903 sspi->rx_word = spi_sirfsoc_rx_word_u32;
904 sspi->tx_word = spi_sirfsoc_tx_word_u32;
910 sspi->word_width = DIV_ROUND_UP(bits_per_word, 8);
911 txfifo_ctrl = (((sspi->fifo_size / 2) &
912 SIRFSOC_SPI_FIFO_THD_MASK(sspi))
914 (sspi->word_width >> 1);
915 rxfifo_ctrl = (((sspi->fifo_size / 2) &
916 SIRFSOC_SPI_FIFO_THD_MASK(sspi))
918 (sspi->word_width >> 1);
919 writel(txfifo_ctrl, sspi->base + sspi->regs->txfifo_ctrl);
920 writel(rxfifo_ctrl, sspi->base + sspi->regs->rxfifo_ctrl);
921 if (sspi->type == SIRF_USP_SPI_P2 ||
922 sspi->type == SIRF_USP_SPI_A7) {
947 sspi->base + sspi->regs->usp_tx_frame_ctrl);
951 sspi->base + sspi->regs->usp_rx_frame_ctrl);
952 writel(readl(sspi->base + sspi->regs->usp_mode2) |
959 sspi->base + sspi->regs->usp_mode2);
961 if (sspi->type == SIRF_REAL_SPI)
962 writel(regval, sspi->base + sspi->regs->spi_ctrl);
964 if (sspi->type == SIRF_REAL_SPI) {
967 sspi->tx_by_cmd = true;
968 writel(readl(sspi->base + sspi->regs->spi_ctrl) |
971 sspi->base + sspi->regs->spi_ctrl);
973 sspi->tx_by_cmd = false;
974 writel(readl(sspi->base + sspi->regs->spi_ctrl) &
976 sspi->base + sspi->regs->spi_ctrl);
981 writel(0, sspi->base + sspi->regs->tx_dma_io_ctrl);
983 sspi->base + sspi->regs->rx_dma_io_ctrl);
987 sspi->base + sspi->regs->tx_dma_io_ctrl);
989 sspi->base + sspi->regs->rx_dma_io_ctrl);
996 struct sirfsoc_spi *sspi;
999 sspi = spi_master_get_devdata(spi->master);
1001 sspi->hw_cs = true;
1003 sspi->hw_cs = false;
1071 struct sirfsoc_spi *sspi;
1084 master = spi_alloc_master(&pdev->dev, sizeof(*sspi));
1091 sspi = spi_master_get_devdata(master);
1092 sspi->fifo_full_offset = ilog2(sspi->fifo_size);
1094 sspi->regs = spi_comp_data->regs;
1095 sspi->type = spi_comp_data->type;
1096 sspi->fifo_level_chk_mask = (sspi->fifo_size / 4) - 1;
1097 sspi->dat_max_frm_len = spi_comp_data->dat_max_frm_len;
1098 sspi->fifo_size = spi_comp_data->fifo_size;
1099 sspi->base = devm_platform_ioremap_resource(pdev, 0);
1100 if (IS_ERR(sspi->base)) {
1101 ret = PTR_ERR(sspi->base);
1110 DRIVER_NAME, sspi);
1114 sspi->bitbang.master = master;
1115 sspi->bitbang.chipselect = spi_sirfsoc_chipselect;
1116 sspi->bitbang.setup_transfer = spi_sirfsoc_setup_transfer;
1117 sspi->bitbang.txrx_bufs = spi_sirfsoc_transfer;
1118 sspi->bitbang.master->setup = spi_sirfsoc_setup;
1119 sspi->bitbang.master->cleanup = spi_sirfsoc_cleanup;
1126 sspi->bitbang.master->dev.of_node = pdev->dev.of_node;
1129 sspi->rx_chan = dma_request_chan(&pdev->dev, "rx");
1130 if (IS_ERR(sspi->rx_chan)) {
1132 ret = PTR_ERR(sspi->rx_chan);
1135 sspi->tx_chan = dma_request_chan(&pdev->dev, "tx");
1136 if (IS_ERR(sspi->tx_chan)) {
1138 ret = PTR_ERR(sspi->tx_chan);
1142 sspi->clk = clk_get(&pdev->dev, NULL);
1143 if (IS_ERR(sspi->clk)) {
1144 ret = PTR_ERR(sspi->clk);
1147 clk_prepare_enable(sspi->clk);
1149 spi_comp_data->hwinit(sspi);
1150 sspi->ctrl_freq = clk_get_rate(sspi->clk);
1152 init_completion(&sspi->rx_done);
1153 init_completion(&sspi->tx_done);
1155 ret = spi_bitbang_start(&sspi->bitbang);
1162 clk_disable_unprepare(sspi->clk);
1163 clk_put(sspi->clk);
1165 dma_release_channel(sspi->tx_chan);
1167 dma_release_channel(sspi->rx_chan);
1177 struct sirfsoc_spi *sspi;
1180 sspi = spi_master_get_devdata(master);
1181 spi_bitbang_stop(&sspi->bitbang);
1182 clk_disable_unprepare(sspi->clk);
1183 clk_put(sspi->clk);
1184 dma_release_channel(sspi->rx_chan);
1185 dma_release_channel(sspi->tx_chan);
1194 struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
1201 clk_disable(sspi->clk);
1208 struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
1210 clk_enable(sspi->clk);
1211 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op);
1212 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->rxfifo_op);
1213 writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->txfifo_op);
1214 writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->rxfifo_op);