Lines Matching defs:regval
734 u32 regval;
738 regval = readl(sspi->base + sspi->regs->spi_ctrl);
742 regval |= SIRFSOC_SPI_CS_IO_OUT;
744 regval &= ~SIRFSOC_SPI_CS_IO_OUT;
748 regval &= ~SIRFSOC_SPI_CS_IO_OUT;
750 regval |= SIRFSOC_SPI_CS_IO_OUT;
753 writel(regval, sspi->base + sspi->regs->spi_ctrl);
757 regval = readl(sspi->base +
762 regval |= SIRFSOC_USP_CS_HIGH_VALUE;
764 regval &= ~(SIRFSOC_USP_CS_HIGH_VALUE);
768 regval &= ~(SIRFSOC_USP_CS_HIGH_VALUE);
770 regval |= SIRFSOC_USP_CS_HIGH_VALUE;
773 writel(regval,
794 u32 regval, usp_mode1;
797 regval = readl(sspi->base + sspi->regs->spi_ctrl);
800 regval |= SIRFSOC_SPI_CS_IDLE_STAT;
803 regval &= ~SIRFSOC_SPI_CS_IDLE_STAT;
807 regval |= SIRFSOC_SPI_TRAN_MSB;
810 regval &= ~SIRFSOC_SPI_TRAN_MSB;
814 regval |= SIRFSOC_SPI_CLK_IDLE_STAT;
817 regval &= ~SIRFSOC_SPI_CLK_IDLE_STAT;
826 regval &= ~SIRFSOC_SPI_DRV_POS_EDGE;
830 regval |= SIRFSOC_SPI_DRV_POS_EDGE;
854 regval |= SIRFSOC_SPI_CS_IO_MODE;
855 writel(regval, sspi->base + sspi->regs->spi_ctrl);
875 u32 regval, txfifo_ctrl, rxfifo_ctrl, tx_frm_ctl, rx_frm_ctl, usp_mode2;
882 usp_mode2 = regval = (sspi->ctrl_freq / (2 * hz)) - 1;
883 if (regval > 0xFFFF || regval < 0) {
889 regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_8;
895 regval |= (bits_per_word == 12) ?
902 regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_32;
962 writel(regval, sspi->base + sspi->regs->spi_ctrl);