Lines Matching defs:sifive_spi_write
99 static void sifive_spi_write(struct sifive_spi *spi, int offset, u32 value)
112 sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
115 sifive_spi_write(spi, SIFIVE_SPI_REG_TXMARK, 1);
116 sifive_spi_write(spi, SIFIVE_SPI_REG_RXMARK, 0);
119 sifive_spi_write(spi, SIFIVE_SPI_REG_DELAY0,
122 sifive_spi_write(spi, SIFIVE_SPI_REG_DELAY1,
127 sifive_spi_write(spi, SIFIVE_SPI_REG_FCTRL, 0);
141 sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);
144 sifive_spi_write(spi, SIFIVE_SPI_REG_CSID, device->chip_select);
147 sifive_spi_write(spi, SIFIVE_SPI_REG_SCKMODE,
161 sifive_spi_write(spi, SIFIVE_SPI_REG_CSMODE, is_high ?
176 sifive_spi_write(spi, SIFIVE_SPI_REG_SCKDIV, cr);
197 sifive_spi_write(spi, SIFIVE_SPI_REG_FMT, cr);
215 sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
233 sifive_spi_write(spi, SIFIVE_SPI_REG_IE, bit);
242 sifive_spi_write(spi, SIFIVE_SPI_REG_TXDATA,
274 sifive_spi_write(spi, SIFIVE_SPI_REG_RXMARK,
354 sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, 0xffffffffU);
356 sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);
424 sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);