Lines Matching refs:ss
84 static void spi_sh_write(struct spi_sh_data *ss, unsigned long data,
87 if (ss->width == 8)
88 iowrite8(data, ss->addr + (offset >> 2));
89 else if (ss->width == 32)
90 iowrite32(data, ss->addr + offset);
93 static unsigned long spi_sh_read(struct spi_sh_data *ss, unsigned long offset)
95 if (ss->width == 8)
96 return ioread8(ss->addr + (offset >> 2));
97 else if (ss->width == 32)
98 return ioread32(ss->addr + offset);
103 static void spi_sh_set_bit(struct spi_sh_data *ss, unsigned long val,
108 tmp = spi_sh_read(ss, offset);
110 spi_sh_write(ss, tmp, offset);
113 static void spi_sh_clear_bit(struct spi_sh_data *ss, unsigned long val,
118 tmp = spi_sh_read(ss, offset);
120 spi_sh_write(ss, tmp, offset);
123 static void clear_fifo(struct spi_sh_data *ss)
125 spi_sh_set_bit(ss, SPI_SH_RSTF, SPI_SH_CR2);
126 spi_sh_clear_bit(ss, SPI_SH_RSTF, SPI_SH_CR2);
129 static int spi_sh_wait_receive_buffer(struct spi_sh_data *ss)
133 while (spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) {
141 static int spi_sh_wait_write_buffer_empty(struct spi_sh_data *ss)
145 while (!(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBE)) {
153 static int spi_sh_send(struct spi_sh_data *ss, struct spi_message *mesg,
163 spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
169 !(spi_sh_read(ss, SPI_SH_CR4) &
171 !(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBF);
173 spi_sh_write(ss, (unsigned long)data[i], SPI_SH_TBR);
175 if (spi_sh_read(ss, SPI_SH_CR4) & SPI_SH_WPABRT) {
177 spi_sh_set_bit(ss, SPI_SH_WPABRT, SPI_SH_CR4);
188 ss->cr1 &= ~SPI_SH_TBE;
189 spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4);
190 ret = wait_event_interruptible_timeout(ss->wait,
191 ss->cr1 & SPI_SH_TBE,
193 if (ret == 0 && !(ss->cr1 & SPI_SH_TBE)) {
201 spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1);
202 spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
204 ss->cr1 &= ~SPI_SH_TBE;
205 spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4);
206 ret = wait_event_interruptible_timeout(ss->wait,
207 ss->cr1 & SPI_SH_TBE,
209 if (ret == 0 && (ss->cr1 & SPI_SH_TBE)) {
218 static int spi_sh_receive(struct spi_sh_data *ss, struct spi_message *mesg,
228 spi_sh_write(ss, SPI_SH_MAX_BYTE, SPI_SH_CR3);
230 spi_sh_write(ss, t->len, SPI_SH_CR3);
232 spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1);
233 spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
235 spi_sh_wait_write_buffer_empty(ss);
240 ss->cr1 &= ~SPI_SH_RBF;
241 spi_sh_set_bit(ss, SPI_SH_RBF, SPI_SH_CR4);
242 ret = wait_event_interruptible_timeout(ss->wait,
243 ss->cr1 & SPI_SH_RBF,
246 spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) {
254 if (spi_sh_wait_receive_buffer(ss))
256 data[i] = (unsigned char)spi_sh_read(ss, SPI_SH_RBR);
265 clear_fifo(ss);
266 spi_sh_write(ss, 1, SPI_SH_CR3);
268 spi_sh_write(ss, 0, SPI_SH_CR3);
276 struct spi_sh_data *ss = container_of(work, struct spi_sh_data, ws);
284 spin_lock_irqsave(&ss->lock, flags);
285 while (!list_empty(&ss->queue)) {
286 mesg = list_entry(ss->queue.next, struct spi_message, queue);
289 spin_unlock_irqrestore(&ss->lock, flags);
297 ret = spi_sh_send(ss, mesg, t);
302 ret = spi_sh_receive(ss, mesg, t);
308 spin_lock_irqsave(&ss->lock, flags);
315 clear_fifo(ss);
316 spi_sh_set_bit(ss, SPI_SH_SSD, SPI_SH_CR1);
319 spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
322 clear_fifo(ss);
324 spin_unlock_irqrestore(&ss->lock, flags);
333 spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
335 clear_fifo(ss);
341 struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
345 spi_sh_write(ss, 0xfe, SPI_SH_CR1); /* SPI sycle stop */
346 spi_sh_write(ss, 0x00, SPI_SH_CR1); /* CR1 init */
347 spi_sh_write(ss, 0x00, SPI_SH_CR3); /* CR3 init */
349 clear_fifo(ss);
352 spi_sh_write(ss, spi_sh_read(ss, SPI_SH_CR2) | 0x07, SPI_SH_CR2);
360 struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
366 spin_lock_irqsave(&ss->lock, flags);
371 spi_sh_clear_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
373 list_add_tail(&mesg->queue, &ss->queue);
374 schedule_work(&ss->ws);
376 spin_unlock_irqrestore(&ss->lock, flags);
383 struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
387 spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
393 struct spi_sh_data *ss = (struct spi_sh_data *)_ss;
396 cr1 = spi_sh_read(ss, SPI_SH_CR1);
398 ss->cr1 |= SPI_SH_TBE;
400 ss->cr1 |= SPI_SH_TBF;
402 ss->cr1 |= SPI_SH_RBE;
404 ss->cr1 |= SPI_SH_RBF;
406 if (ss->cr1) {
407 spi_sh_clear_bit(ss, ss->cr1, SPI_SH_CR4);
408 wake_up(&ss->wait);
416 struct spi_sh_data *ss = platform_get_drvdata(pdev);
418 spi_unregister_master(ss->master);
419 flush_work(&ss->ws);
420 free_irq(ss->irq, ss);
429 struct spi_sh_data *ss;
449 ss = spi_master_get_devdata(master);
450 platform_set_drvdata(pdev, ss);
454 ss->width = 8;
457 ss->width = 32;
463 ss->irq = irq;
464 ss->master = master;
465 ss->addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
466 if (ss->addr == NULL) {
470 INIT_LIST_HEAD(&ss->queue);
471 spin_lock_init(&ss->lock);
472 INIT_WORK(&ss->ws, spi_sh_work);
473 init_waitqueue_head(&ss->wait);
475 ret = request_irq(irq, spi_sh_irq, 0, "spi_sh", ss);
496 free_irq(irq, ss);