Lines Matching defs:hspi
46 static void hspi_write(struct hspi_priv *hspi, int reg, u32 val)
48 iowrite32(val, hspi->addr + reg);
51 static u32 hspi_read(struct hspi_priv *hspi, int reg)
53 return ioread32(hspi->addr + reg);
56 static void hspi_bit_set(struct hspi_priv *hspi, int reg, u32 mask, u32 set)
58 u32 val = hspi_read(hspi, reg);
63 hspi_write(hspi, reg, val);
69 static int hspi_status_check_timeout(struct hspi_priv *hspi, u32 mask, u32 val)
74 if ((mask & hspi_read(hspi, SPSR)) == val)
80 dev_err(hspi->dev, "timeout\n");
88 #define hspi_hw_cs_enable(hspi) hspi_hw_cs_ctrl(hspi, 0)
89 #define hspi_hw_cs_disable(hspi) hspi_hw_cs_ctrl(hspi, 1)
90 static void hspi_hw_cs_ctrl(struct hspi_priv *hspi, int hi)
92 hspi_bit_set(hspi, SPSCR, (1 << 6), (hi) << 6);
95 static void hspi_hw_setup(struct hspi_priv *hspi,
100 struct device *dev = hspi->dev;
111 rate = clk_get_rate(hspi->clk);
138 hspi_write(hspi, SPCR, spcr);
139 hspi_write(hspi, SPSR, 0x0);
140 hspi_write(hspi, SPSCR, 0x21); /* master mode / CS control */
146 struct hspi_priv *hspi = spi_controller_get_devdata(ctlr);
154 dev_dbg(hspi->dev, "%s\n", __func__);
161 hspi_hw_setup(hspi, msg, t);
162 hspi_hw_cs_enable(hspi);
170 ret = hspi_status_check_timeout(hspi, 0x1, 0);
178 hspi_write(hspi, SPTBR, tx);
181 ret = hspi_status_check_timeout(hspi, 0x4, 0x4);
185 rx = hspi_read(hspi, SPRBR);
197 hspi_hw_cs_disable(hspi);
205 hspi_hw_cs_disable(hspi);
216 struct hspi_priv *hspi;
227 ctlr = spi_alloc_master(&pdev->dev, sizeof(*hspi));
238 hspi = spi_controller_get_devdata(ctlr);
239 platform_set_drvdata(pdev, hspi);
241 /* init hspi */
242 hspi->ctlr = ctlr;
243 hspi->dev = &pdev->dev;
244 hspi->clk = clk;
245 hspi->addr = devm_ioremap(hspi->dev,
247 if (!hspi->addr) {
281 struct hspi_priv *hspi = platform_get_drvdata(pdev);
285 clk_put(hspi->clk);
291 { .compatible = "renesas,hspi", },
300 .name = "sh-hspi",
309 MODULE_ALIAS("platform:sh-hspi");