Lines Matching refs:val
201 u32 val;
205 val = readl(regs + S3C64XX_SPI_CH_CFG);
206 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
207 writel(val, regs + S3C64XX_SPI_CH_CFG);
209 val = readl(regs + S3C64XX_SPI_CH_CFG);
210 val |= S3C64XX_SPI_CH_SW_RST;
211 val &= ~S3C64XX_SPI_CH_HS_EN;
212 writel(val, regs + S3C64XX_SPI_CH_CFG);
217 val = readl(regs + S3C64XX_SPI_STATUS);
218 } while (TX_FIFO_LVL(val, sdd) && loops--);
226 val = readl(regs + S3C64XX_SPI_STATUS);
227 if (RX_FIFO_LVL(val, sdd))
236 val = readl(regs + S3C64XX_SPI_CH_CFG);
237 val &= ~S3C64XX_SPI_CH_SW_RST;
238 writel(val, regs + S3C64XX_SPI_CH_CFG);
240 val = readl(regs + S3C64XX_SPI_MODE_CFG);
241 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
242 writel(val, regs + S3C64XX_SPI_MODE_CFG);
450 unsigned long val = 1;
457 val = msecs_to_loops(timeout_ms);
461 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
471 unsigned long val;
480 val = msecs_to_jiffies(ms) + 10;
481 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
492 if (val && !xfer->rx_buf) {
493 val = msecs_to_loops(10);
497 && --val) {
505 if (!val)
515 unsigned long val;
526 val = msecs_to_loops(ms);
529 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
531 if (!val)
581 u32 val;
585 val = readl(regs + S3C64XX_SPI_CLK_CFG);
586 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
587 writel(val, regs + S3C64XX_SPI_CLK_CFG);
591 val = readl(regs + S3C64XX_SPI_CH_CFG);
592 val &= ~(S3C64XX_SPI_CH_SLAVE |
597 val |= S3C64XX_SPI_CPOL_L;
600 val |= S3C64XX_SPI_CPHA_B;
602 writel(val, regs + S3C64XX_SPI_CH_CFG);
605 val = readl(regs + S3C64XX_SPI_MODE_CFG);
606 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
611 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
612 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
615 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
616 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
619 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
620 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
624 writel(val, regs + S3C64XX_SPI_MODE_CFG);
634 val = readl(regs + S3C64XX_SPI_CLK_CFG);
635 val &= ~S3C64XX_SPI_PSR_MASK;
636 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
638 writel(val, regs + S3C64XX_SPI_CLK_CFG);
641 val = readl(regs + S3C64XX_SPI_CLK_CFG);
642 val |= S3C64XX_SPI_ENCLK_ENABLE;
643 writel(val, regs + S3C64XX_SPI_CLK_CFG);
955 unsigned int val, clr = 0;
957 val = readl(sdd->regs + S3C64XX_SPI_STATUS);
959 if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
963 if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
967 if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
971 if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
987 unsigned int val;
1006 val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
1010 writel(val, regs + S3C64XX_SPI_PENDING_CLR);
1015 val = readl(regs + S3C64XX_SPI_MODE_CFG);
1016 val &= ~S3C64XX_SPI_MODE_4BURST;
1017 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1018 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1019 writel(val, regs + S3C64XX_SPI_MODE_CFG);