Lines Matching refs:rspi
26 #include <linux/spi/rspi.h>
199 static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
201 iowrite8(data, rspi->addr + offset);
204 static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset)
206 iowrite16(data, rspi->addr + offset);
209 static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset)
211 iowrite32(data, rspi->addr + offset);
214 static u8 rspi_read8(const struct rspi_data *rspi, u16 offset)
216 return ioread8(rspi->addr + offset);
219 static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
221 return ioread16(rspi->addr + offset);
224 static void rspi_write_data(const struct rspi_data *rspi, u16 data)
226 if (rspi->byte_access)
227 rspi_write8(rspi, data, RSPI_SPDR);
229 rspi_write16(rspi, data, RSPI_SPDR);
232 static u16 rspi_read_data(const struct rspi_data *rspi)
234 if (rspi->byte_access)
235 return rspi_read8(rspi, RSPI_SPDR);
237 return rspi_read16(rspi, RSPI_SPDR);
242 int (*set_config_register)(struct rspi_data *rspi, int access_size);
253 static void rspi_set_rate(struct rspi_data *rspi)
258 clksrc = clk_get_rate(rspi->clk);
259 spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz) - 1;
265 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
266 rspi->spcmd |= SPCMD_BRDV(brdv);
267 rspi->speed_hz = DIV_ROUND_UP(clksrc, (2U << brdv) * (spbr + 1));
273 static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
276 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
279 rspi_set_rate(rspi);
282 rspi_write8(rspi, 0, RSPI_SPDCR);
283 rspi->byte_access = 0;
286 rspi_write8(rspi, 0x00, RSPI_SPCKD);
287 rspi_write8(rspi, 0x00, RSPI_SSLND);
288 rspi_write8(rspi, 0x00, RSPI_SPND);
291 rspi_write8(rspi, 0x00, RSPI_SPCR2);
294 rspi_write8(rspi, 0, RSPI_SPSCR);
295 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
296 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
299 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
307 static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
310 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
313 rspi_set_rate(rspi);
316 rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR);
317 rspi->byte_access = 1;
320 rspi_write8(rspi, 0x00, RSPI_SPCKD);
321 rspi_write8(rspi, 0x00, RSPI_SSLND);
322 rspi_write8(rspi, 0x00, RSPI_SPND);
325 rspi_write8(rspi, 0, RSPI_SPSCR);
326 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
327 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
330 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
338 static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
344 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
347 clksrc = clk_get_rate(rspi->clk);
348 if (rspi->speed_hz >= clksrc) {
350 rspi->speed_hz = clksrc;
352 spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz);
358 rspi->speed_hz = DIV_ROUND_UP(clksrc, (2U << brdv) * spbr);
360 rspi_write8(rspi, spbr, RSPI_SPBR);
361 rspi->spcmd |= SPCMD_BRDV(brdv);
364 rspi_write8(rspi, 0, RSPI_SPDCR);
365 rspi->byte_access = 1;
368 rspi_write8(rspi, 0x00, RSPI_SPCKD);
369 rspi_write8(rspi, 0x00, RSPI_SSLND);
370 rspi_write8(rspi, 0x00, RSPI_SPND);
374 rspi->spcmd |= SPCMD_SPB_8BIT;
376 rspi->spcmd |= SPCMD_SPB_16BIT;
378 rspi->spcmd |= SPCMD_SPB_32BIT;
380 rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN;
383 rspi_write32(rspi, 0, QSPI_SPBMUL0);
386 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
388 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
391 rspi_write8(rspi, 0, RSPI_SPSCR);
392 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
395 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
400 static void qspi_update(const struct rspi_data *rspi, u8 mask, u8 val, u8 reg)
404 data = rspi_read8(rspi, reg);
407 rspi_write8(rspi, data, reg);
410 static unsigned int qspi_set_send_trigger(struct rspi_data *rspi,
419 qspi_update(rspi, SPBFCR_TXTRG_MASK,
423 qspi_update(rspi, SPBFCR_TXTRG_MASK,
430 static int qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
438 qspi_update(rspi, SPBFCR_RXTRG_MASK,
442 qspi_update(rspi, SPBFCR_RXTRG_MASK,
448 static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable)
450 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
453 static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable)
455 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
458 static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
463 rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
464 if (rspi->spsr & wait_mask)
467 rspi_enable_irq(rspi, enable_bit);
468 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
469 if (ret == 0 && !(rspi->spsr & wait_mask))
475 static inline int rspi_wait_for_tx_empty(struct rspi_data *rspi)
477 return rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
480 static inline int rspi_wait_for_rx_full(struct rspi_data *rspi)
482 return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE);
485 static int rspi_data_out(struct rspi_data *rspi, u8 data)
487 int error = rspi_wait_for_tx_empty(rspi);
489 dev_err(&rspi->ctlr->dev, "transmit timeout\n");
492 rspi_write_data(rspi, data);
496 static int rspi_data_in(struct rspi_data *rspi)
501 error = rspi_wait_for_rx_full(rspi);
503 dev_err(&rspi->ctlr->dev, "receive timeout\n");
506 data = rspi_read_data(rspi);
510 static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx,
515 int ret = rspi_data_out(rspi, *tx++);
520 int ret = rspi_data_in(rspi);
532 struct rspi_data *rspi = arg;
534 rspi->dma_callbacked = 1;
535 wake_up_interruptible(&rspi->wait);
538 static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx,
549 desc_rx = dmaengine_prep_slave_sg(rspi->ctlr->dma_rx, rx->sgl,
558 desc_rx->callback_param = rspi;
569 desc_tx = dmaengine_prep_slave_sg(rspi->ctlr->dma_tx, tx->sgl,
582 desc_tx->callback_param = rspi;
598 disable_irq(other_irq = rspi->tx_irq);
599 if (rx && rspi->rx_irq != other_irq)
600 disable_irq(rspi->rx_irq);
602 rspi_enable_irq(rspi, irq_mask);
603 rspi->dma_callbacked = 0;
607 dma_async_issue_pending(rspi->ctlr->dma_rx);
609 dma_async_issue_pending(rspi->ctlr->dma_tx);
611 ret = wait_event_interruptible_timeout(rspi->wait,
612 rspi->dma_callbacked, HZ);
613 if (ret > 0 && rspi->dma_callbacked) {
616 dmaengine_synchronize(rspi->ctlr->dma_tx);
618 dmaengine_synchronize(rspi->ctlr->dma_rx);
621 dev_err(&rspi->ctlr->dev, "DMA timeout\n");
625 dmaengine_terminate_all(rspi->ctlr->dma_tx);
627 dmaengine_terminate_all(rspi->ctlr->dma_rx);
630 rspi_disable_irq(rspi, irq_mask);
633 enable_irq(rspi->tx_irq);
634 if (rx && rspi->rx_irq != other_irq)
635 enable_irq(rspi->rx_irq);
641 dmaengine_terminate_all(rspi->ctlr->dma_rx);
644 dev_warn_once(&rspi->ctlr->dev,
650 static void rspi_receive_init(const struct rspi_data *rspi)
654 spsr = rspi_read8(rspi, RSPI_SPSR);
656 rspi_read_data(rspi); /* dummy read */
658 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
662 static void rspi_rz_receive_init(const struct rspi_data *rspi)
664 rspi_receive_init(rspi);
665 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR);
666 rspi_write8(rspi, 0, RSPI_SPBFCR);
669 static void qspi_receive_init(const struct rspi_data *rspi)
673 spsr = rspi_read8(rspi, RSPI_SPSR);
675 rspi_read_data(rspi); /* dummy read */
676 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
677 rspi_write8(rspi, 0, QSPI_SPBFCR);
680 static bool __rspi_can_dma(const struct rspi_data *rspi,
683 return xfer->len > rspi->ops->fifo_size;
689 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
691 return __rspi_can_dma(rspi, xfer);
694 static int rspi_dma_check_then_transfer(struct rspi_data *rspi,
697 if (!rspi->ctlr->can_dma || !__rspi_can_dma(rspi, xfer))
701 return rspi_dma_transfer(rspi, &xfer->tx_sg,
705 static int rspi_common_transfer(struct rspi_data *rspi,
710 xfer->effective_speed_hz = rspi->speed_hz;
712 ret = rspi_dma_check_then_transfer(rspi, xfer);
716 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
721 rspi_wait_for_tx_empty(rspi);
729 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
732 spcr = rspi_read8(rspi, RSPI_SPCR);
734 rspi_receive_init(rspi);
739 rspi_write8(rspi, spcr, RSPI_SPCR);
741 return rspi_common_transfer(rspi, xfer);
748 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
750 rspi_rz_receive_init(rspi);
752 return rspi_common_transfer(rspi, xfer);
755 static int qspi_trigger_transfer_out_in(struct rspi_data *rspi, const u8 *tx,
762 n = qspi_set_send_trigger(rspi, len);
763 qspi_set_receive_trigger(rspi, len);
764 ret = rspi_wait_for_tx_empty(rspi);
766 dev_err(&rspi->ctlr->dev, "transmit timeout\n");
770 rspi_write_data(rspi, *tx++);
772 ret = rspi_wait_for_rx_full(rspi);
774 dev_err(&rspi->ctlr->dev, "receive timeout\n");
778 *rx++ = rspi_read_data(rspi);
786 static int qspi_transfer_out_in(struct rspi_data *rspi,
791 qspi_receive_init(rspi);
793 ret = rspi_dma_check_then_transfer(rspi, xfer);
797 return qspi_trigger_transfer_out_in(rspi, xfer->tx_buf,
801 static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
808 if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) {
809 ret = rspi_dma_transfer(rspi, &xfer->tx_sg, NULL);
815 len = qspi_set_send_trigger(rspi, n);
816 ret = rspi_wait_for_tx_empty(rspi);
818 dev_err(&rspi->ctlr->dev, "transmit timeout\n");
822 rspi_write_data(rspi, *tx++);
828 rspi_wait_for_tx_empty(rspi);
833 static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
840 if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) {
841 int ret = rspi_dma_transfer(rspi, NULL, &xfer->rx_sg);
847 len = qspi_set_receive_trigger(rspi, n);
848 ret = rspi_wait_for_rx_full(rspi);
850 dev_err(&rspi->ctlr->dev, "receive timeout\n");
854 *rx++ = rspi_read_data(rspi);
865 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
867 xfer->effective_speed_hz = rspi->speed_hz;
869 return qspi_transfer_out_in(rspi, xfer);
872 return qspi_transfer_out(rspi, xfer);
875 return qspi_transfer_in(rspi, xfer);
878 return qspi_transfer_out_in(rspi, xfer);
906 static int qspi_setup_sequencer(struct rspi_data *rspi,
923 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
933 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i));
940 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
941 rspi_write8(rspi, i - 1, RSPI_SPSCR);
949 struct rspi_data *rspi = spi_controller_get_devdata(spi->controller);
955 pm_runtime_get_sync(&rspi->pdev->dev);
956 spin_lock_irq(&rspi->lock);
958 sslp = rspi_read8(rspi, RSPI_SSLP);
963 rspi_write8(rspi, sslp, RSPI_SSLP);
965 spin_unlock_irq(&rspi->lock);
966 pm_runtime_put(&rspi->pdev->dev);
973 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
988 rspi->speed_hz = spi->max_speed_hz;
990 if (xfer->speed_hz < rspi->speed_hz)
991 rspi->speed_hz = xfer->speed_hz;
994 rspi->spcmd = SPCMD_SSLKP;
996 rspi->spcmd |= SPCMD_CPOL;
998 rspi->spcmd |= SPCMD_CPHA;
1000 rspi->spcmd |= SPCMD_LSBF;
1003 rspi->spcmd |= SPCMD_SSLA(spi->cs_gpiod ? rspi->ctlr->unused_native_cs
1007 rspi->sppcr = 0;
1009 rspi->sppcr |= SPPCR_SPLP;
1011 rspi->ops->set_config_register(rspi, 8);
1016 ret = qspi_setup_sequencer(rspi, msg);
1022 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
1029 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
1032 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
1035 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
1036 rspi_write8(rspi, 0, RSPI_SPSCR);
1042 struct rspi_data *rspi = _sr;
1047 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1055 rspi_disable_irq(rspi, disable_irq);
1056 wake_up(&rspi->wait);
1064 struct rspi_data *rspi = _sr;
1067 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1069 rspi_disable_irq(rspi, SPCR_SPRIE);
1070 wake_up(&rspi->wait);
1079 struct rspi_data *rspi = _sr;
1082 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1084 rspi_disable_irq(rspi, SPCR_SPTIE);
1085 wake_up(&rspi->wait);
1176 struct rspi_data *rspi = platform_get_drvdata(pdev);
1178 rspi_release_dma(rspi->ctlr);
1219 { .compatible = "renesas,rspi", .data = &rspi_ops },
1221 { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops },
1268 struct rspi_data *rspi;
1292 rspi = spi_controller_get_devdata(ctlr);
1293 platform_set_drvdata(pdev, rspi);
1294 rspi->ops = ops;
1295 rspi->ctlr = ctlr;
1298 rspi->addr = devm_ioremap_resource(&pdev->dev, res);
1299 if (IS_ERR(rspi->addr)) {
1300 ret = PTR_ERR(rspi->addr);
1304 rspi->clk = devm_clk_get(&pdev->dev, NULL);
1305 if (IS_ERR(rspi->clk)) {
1307 ret = PTR_ERR(rspi->clk);
1311 rspi->pdev = pdev;
1314 init_waitqueue_head(&rspi->wait);
1315 spin_lock_init(&rspi->lock);
1325 clksrc = clk_get_rate(rspi->clk);
1331 ctlr->max_native_cs = rspi->ops->num_hw_ss;
1339 rspi->rx_irq = rspi->tx_irq = ret;
1341 rspi->rx_irq = ret;
1344 rspi->tx_irq = ret;
1347 if (rspi->rx_irq == rspi->tx_irq) {
1349 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux,
1350 "mux", rspi);
1353 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx,
1354 "rx", rspi);
1356 ret = rspi_request_irq(&pdev->dev, rspi->tx_irq,
1357 rspi_irq_tx, "tx", rspi);
1389 { "rspi", (kernel_ulong_t)&rspi_ops },
1398 struct rspi_data *rspi = dev_get_drvdata(dev);
1400 return spi_controller_suspend(rspi->ctlr);
1405 struct rspi_data *rspi = dev_get_drvdata(dev);
1407 return spi_controller_resume(rspi->ctlr);
1431 MODULE_ALIAS("platform:rspi");