Lines Matching refs:controller
156 static inline bool spi_qup_is_flag_set(struct spi_qup *controller, u32 flag)
158 u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL);
172 static inline unsigned int spi_qup_len(struct spi_qup *controller)
174 return controller->n_words * controller->w_size;
177 static inline bool spi_qup_is_valid_state(struct spi_qup *controller)
179 u32 opstate = readl_relaxed(controller->base + QUP_STATE);
184 static int spi_qup_set_state(struct spi_qup *controller, u32 state)
190 while (!spi_qup_is_valid_state(controller)) {
199 dev_dbg(controller->dev, "invalid state for %ld,us %d\n",
202 cur_state = readl_relaxed(controller->base + QUP_STATE);
209 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
210 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
214 writel_relaxed(cur_state, controller->base + QUP_STATE);
218 while (!spi_qup_is_valid_state(controller)) {
229 static void spi_qup_read_from_fifo(struct spi_qup *controller, u32 num_words)
231 u8 *rx_buf = controller->rx_buf;
237 word = readl_relaxed(controller->base + QUP_INPUT_FIFO);
239 num_bytes = min_t(int, spi_qup_len(controller) -
240 controller->rx_bytes,
241 controller->w_size);
244 controller->rx_bytes += num_bytes;
248 for (i = 0; i < num_bytes; i++, controller->rx_bytes++) {
256 shift *= (controller->w_size - i - 1);
257 rx_buf[controller->rx_bytes] = word >> shift;
262 static void spi_qup_read(struct spi_qup *controller, u32 *opflags)
265 bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK;
267 remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->rx_bytes,
268 controller->w_size);
269 words_per_block = controller->in_blk_sz >> 2;
274 controller->base + QUP_OPERATIONAL);
283 if (!spi_qup_is_flag_set(controller,
291 spi_qup_read_from_fifo(controller, num_words);
296 if (is_block_mode && !spi_qup_is_flag_set(controller,
310 *opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
313 controller->base + QUP_OPERATIONAL);
317 static void spi_qup_write_to_fifo(struct spi_qup *controller, u32 num_words)
319 const u8 *tx_buf = controller->tx_buf;
326 num_bytes = min_t(int, spi_qup_len(controller) -
327 controller->tx_bytes,
328 controller->w_size);
331 data = tx_buf[controller->tx_bytes + i];
335 controller->tx_bytes += num_bytes;
337 writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO);
348 static void spi_qup_write(struct spi_qup *controller)
350 bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK;
353 remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->tx_bytes,
354 controller->w_size);
355 words_per_block = controller->out_blk_sz >> 2;
360 controller->base + QUP_OPERATIONAL);
370 if (spi_qup_is_flag_set(controller,
377 spi_qup_write_to_fifo(controller, num_words);
382 if (is_block_mode && !spi_qup_is_flag_set(controller,
579 static bool spi_qup_data_pending(struct spi_qup *controller)
583 remainder_tx = DIV_ROUND_UP(spi_qup_len(controller) -
584 controller->tx_bytes, controller->w_size);
586 remainder_rx = DIV_ROUND_UP(spi_qup_len(controller) -
587 controller->rx_bytes, controller->w_size);
594 struct spi_qup *controller = dev_id;
599 qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS);
600 spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS);
601 opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
603 writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS);
604 writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS);
608 dev_warn(controller->dev, "OUTPUT_OVER_RUN\n");
610 dev_warn(controller->dev, "INPUT_UNDER_RUN\n");
612 dev_warn(controller->dev, "OUTPUT_UNDER_RUN\n");
614 dev_warn(controller->dev, "INPUT_OVER_RUN\n");
621 dev_warn(controller->dev, "CLK_OVER_RUN\n");
623 dev_warn(controller->dev, "CLK_UNDER_RUN\n");
628 spin_lock_irqsave(&controller->lock, flags);
629 if (!controller->error)
630 controller->error = error;
631 spin_unlock_irqrestore(&controller->lock, flags);
633 if (spi_qup_is_dma_xfer(controller->mode)) {
634 writel_relaxed(opflags, controller->base + QUP_OPERATIONAL);
637 spi_qup_read(controller, &opflags);
640 spi_qup_write(controller);
642 if (!spi_qup_data_pending(controller))
643 complete(&controller->done);
647 complete(&controller->done);
650 if (!spi_qup_is_dma_xfer(controller->mode)) {
651 if (spi_qup_data_pending(controller))
654 complete(&controller->done);
663 struct spi_qup *controller = spi_master_get_devdata(spi->master);
666 if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {
667 dev_err(controller->dev, "too big size for loopback %d > %d\n",
668 xfer->len, controller->in_fifo_sz);
672 ret = clk_set_rate(controller->cclk, xfer->speed_hz);
674 dev_err(controller->dev, "fail to set frequency %d",
679 controller->w_size = DIV_ROUND_UP(xfer->bits_per_word, 8);
680 controller->n_words = xfer->len / controller->w_size;
682 if (controller->n_words <= (controller->in_fifo_sz / sizeof(u32)))
683 controller->mode = QUP_IO_M_MODE_FIFO;
687 controller->mode = QUP_IO_M_MODE_BAM;
689 controller->mode = QUP_IO_M_MODE_BLOCK;
697 struct spi_qup *controller = spi_master_get_devdata(spi->master);
701 spin_lock_irqsave(&controller->lock, flags);
702 controller->xfer = xfer;
703 controller->error = 0;
704 controller->rx_bytes = 0;
705 controller->tx_bytes = 0;
706 spin_unlock_irqrestore(&controller->lock, flags);
709 if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
710 dev_err(controller->dev, "cannot set RESET state\n");
714 switch (controller->mode) {
716 writel_relaxed(controller->n_words,
717 controller->base + QUP_MX_READ_CNT);
718 writel_relaxed(controller->n_words,
719 controller->base + QUP_MX_WRITE_CNT);
721 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
722 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
725 writel_relaxed(controller->n_words,
726 controller->base + QUP_MX_INPUT_CNT);
727 writel_relaxed(controller->n_words,
728 controller->base + QUP_MX_OUTPUT_CNT);
730 writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
731 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
733 if (!controller->qup_v1) {
736 input_cnt = controller->base + QUP_MX_INPUT_CNT;
746 writel_relaxed(controller->n_words, input_cnt);
748 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
752 reinit_completion(&controller->done);
753 writel_relaxed(controller->n_words,
754 controller->base + QUP_MX_INPUT_CNT);
755 writel_relaxed(controller->n_words,
756 controller->base + QUP_MX_OUTPUT_CNT);
758 writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
759 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
762 dev_err(controller->dev, "unknown mode = %d\n",
763 controller->mode);
767 iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
771 if (!spi_qup_is_dma_xfer(controller->mode))
776 iomode |= (controller->mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT);
777 iomode |= (controller->mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT);
779 writel_relaxed(iomode, controller->base + QUP_IO_M_MODES);
781 control = readl_relaxed(controller->base + SPI_IO_CONTROL);
788 writel_relaxed(control, controller->base + SPI_IO_CONTROL);
790 config = readl_relaxed(controller->base + SPI_CONFIG);
811 writel_relaxed(config, controller->base + SPI_CONFIG);
813 config = readl_relaxed(controller->base + QUP_CONFIG);
818 if (spi_qup_is_dma_xfer(controller->mode)) {
825 writel_relaxed(config, controller->base + QUP_CONFIG);
828 if (!controller->qup_v1) {
836 if (spi_qup_is_dma_xfer(controller->mode))
839 writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK);
849 struct spi_qup *controller = spi_master_get_devdata(master);
862 reinit_completion(&controller->done);
864 spin_lock_irqsave(&controller->lock, flags);
865 controller->xfer = xfer;
866 controller->error = 0;
867 controller->rx_bytes = 0;
868 controller->tx_bytes = 0;
869 spin_unlock_irqrestore(&controller->lock, flags);
871 if (spi_qup_is_dma_xfer(controller->mode))
876 spi_qup_set_state(controller, QUP_STATE_RESET);
877 spin_lock_irqsave(&controller->lock, flags);
879 ret = controller->error;
880 spin_unlock_irqrestore(&controller->lock, flags);
882 if (ret && spi_qup_is_dma_xfer(controller->mode))
979 struct spi_qup *controller;
983 controller = spi_master_get_devdata(spi->master);
984 spi_ioc = readl_relaxed(controller->base + SPI_IO_CONTROL);
992 writel_relaxed(spi_ioc, controller->base + SPI_IO_CONTROL);
999 struct spi_qup *controller;
1058 controller = spi_master_get_devdata(master);
1060 controller->dev = dev;
1061 controller->base = base;
1062 controller->iclk = iclk;
1063 controller->cclk = cclk;
1064 controller->irq = irq;
1072 controller->qup_v1 = (uintptr_t)of_device_get_match_data(dev);
1074 if (!controller->qup_v1)
1077 spin_lock_init(&controller->lock);
1078 init_completion(&controller->done);
1097 controller->out_blk_sz = size * 16;
1099 controller->out_blk_sz = 4;
1103 controller->in_blk_sz = size * 16;
1105 controller->in_blk_sz = 4;
1108 controller->out_fifo_sz = controller->out_blk_sz * (2 << size);
1111 controller->in_fifo_sz = controller->in_blk_sz * (2 << size);
1114 controller->in_blk_sz, controller->in_fifo_sz,
1115 controller->out_blk_sz, controller->out_fifo_sz);
1119 ret = spi_qup_set_state(controller, QUP_STATE_RESET);
1128 if (!controller->qup_v1)
1135 if (controller->qup_v1)
1144 IRQF_TRIGGER_HIGH, pdev->name, controller);
1175 struct spi_qup *controller = spi_master_get_devdata(master);
1179 config = readl(controller->base + QUP_CONFIG);
1181 writel_relaxed(config, controller->base + QUP_CONFIG);
1183 clk_disable_unprepare(controller->cclk);
1184 clk_disable_unprepare(controller->iclk);
1192 struct spi_qup *controller = spi_master_get_devdata(master);
1196 ret = clk_prepare_enable(controller->iclk);
1200 ret = clk_prepare_enable(controller->cclk);
1202 clk_disable_unprepare(controller->iclk);
1207 config = readl_relaxed(controller->base + QUP_CONFIG);
1209 writel_relaxed(config, controller->base + QUP_CONFIG);
1218 struct spi_qup *controller = spi_master_get_devdata(master);
1230 ret = spi_qup_set_state(controller, QUP_STATE_RESET);
1234 clk_disable_unprepare(controller->cclk);
1235 clk_disable_unprepare(controller->iclk);
1242 struct spi_qup *controller = spi_master_get_devdata(master);
1245 ret = clk_prepare_enable(controller->iclk);
1249 ret = clk_prepare_enable(controller->cclk);
1251 clk_disable_unprepare(controller->iclk);
1255 ret = spi_qup_set_state(controller, QUP_STATE_RESET);
1266 clk_disable_unprepare(controller->cclk);
1267 clk_disable_unprepare(controller->iclk);
1275 struct spi_qup *controller = spi_master_get_devdata(master);
1281 ret = spi_qup_set_state(controller, QUP_STATE_RESET);
1283 dev_warn(&pdev->dev, "failed to reset controller (%pe)\n",
1286 clk_disable_unprepare(controller->cclk);
1287 clk_disable_unprepare(controller->iclk);