Lines Matching refs:base
126 void __iomem *base;
158 u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL);
179 u32 opstate = readl_relaxed(controller->base + QUP_STATE);
202 cur_state = readl_relaxed(controller->base + QUP_STATE);
209 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
210 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
214 writel_relaxed(cur_state, controller->base + QUP_STATE);
237 word = readl_relaxed(controller->base + QUP_INPUT_FIFO);
274 controller->base + QUP_OPERATIONAL);
310 *opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
313 controller->base + QUP_OPERATIONAL);
337 writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO);
360 controller->base + QUP_OPERATIONAL);
599 qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS);
600 spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS);
601 opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
603 writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS);
604 writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS);
634 writel_relaxed(opflags, controller->base + QUP_OPERATIONAL);
717 controller->base + QUP_MX_READ_CNT);
719 controller->base + QUP_MX_WRITE_CNT);
721 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
722 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
726 controller->base + QUP_MX_INPUT_CNT);
728 controller->base + QUP_MX_OUTPUT_CNT);
730 writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
731 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
736 input_cnt = controller->base + QUP_MX_INPUT_CNT;
748 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
754 controller->base + QUP_MX_INPUT_CNT);
756 controller->base + QUP_MX_OUTPUT_CNT);
758 writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
759 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
767 iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
779 writel_relaxed(iomode, controller->base + QUP_IO_M_MODES);
781 control = readl_relaxed(controller->base + SPI_IO_CONTROL);
788 writel_relaxed(control, controller->base + SPI_IO_CONTROL);
790 config = readl_relaxed(controller->base + SPI_CONFIG);
811 writel_relaxed(config, controller->base + SPI_CONFIG);
813 config = readl_relaxed(controller->base + QUP_CONFIG);
825 writel_relaxed(config, controller->base + QUP_CONFIG);
839 writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK);
926 static int spi_qup_init_dma(struct spi_master *master, resource_size_t base)
948 rx_conf->src_addr = base + QUP_INPUT_FIFO;
953 tx_conf->dst_addr = base + QUP_OUTPUT_FIFO;
984 spi_ioc = readl_relaxed(controller->base + SPI_IO_CONTROL);
992 writel_relaxed(spi_ioc, controller->base + SPI_IO_CONTROL);
1002 void __iomem *base;
1008 base = devm_ioremap_resource(dev, res);
1009 if (IS_ERR(base))
1010 return PTR_ERR(base);
1061 controller->base = base;
1093 iomode = readl_relaxed(base + QUP_IO_M_MODES);
1117 writel_relaxed(1, base + QUP_SW_RESET);
1125 writel_relaxed(0, base + QUP_OPERATIONAL);
1126 writel_relaxed(0, base + QUP_IO_M_MODES);
1129 writel_relaxed(0, base + QUP_OPERATIONAL_MASK);
1132 base + SPI_ERROR_FLAGS_EN);
1138 base + QUP_ERROR_FLAGS_EN);
1140 writel_relaxed(0, base + SPI_CONFIG);
1141 writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL);
1179 config = readl(controller->base + QUP_CONFIG);
1181 writel_relaxed(config, controller->base + QUP_CONFIG);
1207 config = readl_relaxed(controller->base + QUP_CONFIG);
1209 writel_relaxed(config, controller->base + QUP_CONFIG);