Lines Matching refs:sccr1_reg
246 u32 *sccr1_reg)
261 *sccr1_reg &= ~mask;
265 u32 *sccr1_reg, u32 threshold)
269 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
272 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);
275 *sccr1_reg |= SSCR1_RxTresh(threshold);
603 u32 sccr1_reg;
605 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
608 sccr1_reg &= ~QUARK_X1000_SSCR1_RFT;
611 sccr1_reg &= ~CE4100_SSCR1_RFT;
614 sccr1_reg &= ~SSCR1_RFT;
617 sccr1_reg |= chip->threshold;
618 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
688 u32 sccr1_reg;
690 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
691 sccr1_reg &= ~SSCR1_TIE;
700 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
716 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
718 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
741 u32 sccr1_reg;
764 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
767 if (!(sccr1_reg & SSCR1_TIE))
771 if (!(sccr1_reg & SSCR1_TINTE))
777 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
778 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);