Lines Matching defs:drv_data
78 /* LPSS offset from drv_data->ioaddr */
80 /* Register offsets from drv_data->lpss_base or -1 */
171 *lpss_get_config(const struct driver_data *drv_data)
173 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
176 static bool is_lpss_ssp(const struct driver_data *drv_data)
178 switch (drv_data->ssp_type) {
191 static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
193 return drv_data->ssp_type == QUARK_X1000_SSP;
196 static bool is_mmp2_ssp(const struct driver_data *drv_data)
198 return drv_data->ssp_type == MMP2_SSP;
201 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
203 switch (drv_data->ssp_type) {
214 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
216 switch (drv_data->ssp_type) {
226 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
230 switch (drv_data->ssp_type) {
242 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
245 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
250 switch (drv_data->ssp_type) {
264 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
267 switch (drv_data->ssp_type) {
280 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
283 switch (drv_data->ssp_type) {
302 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
304 WARN_ON(!drv_data->lpss_base);
305 return readl(drv_data->lpss_base + offset);
308 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
311 WARN_ON(!drv_data->lpss_base);
312 writel(value, drv_data->lpss_base + offset);
317 * @drv_data: pointer to the driver private data
322 static void lpss_ssp_setup(struct driver_data *drv_data)
327 config = lpss_get_config(drv_data);
328 drv_data->lpss_base = drv_data->ioaddr + config->offset;
331 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
334 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
337 if (drv_data->controller_info->enable_dma) {
338 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
341 value = __lpss_ssp_read_priv(drv_data,
344 __lpss_ssp_write_priv(drv_data,
353 struct driver_data *drv_data =
360 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
374 __lpss_ssp_write_priv(drv_data,
377 (drv_data->controller->max_speed_hz / 2));
383 struct driver_data *drv_data =
388 config = lpss_get_config(drv_data);
393 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
398 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
408 clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE);
412 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value);
413 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate);
420 struct driver_data *drv_data =
423 if (drv_data->ssp_type == CE4100_SSP) {
424 pxa2xx_spi_write(drv_data, SSSR, chip->frm);
438 if (is_lpss_ssp(drv_data))
445 struct driver_data *drv_data =
449 if (drv_data->ssp_type == CE4100_SSP)
454 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
468 if (is_lpss_ssp(drv_data))
480 int pxa2xx_spi_flush(struct driver_data *drv_data)
485 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
486 pxa2xx_spi_read(drv_data, SSDR);
487 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
488 write_SSSR_CS(drv_data, SSSR_ROR);
493 static void pxa2xx_spi_off(struct driver_data *drv_data)
496 if (is_mmp2_ssp(drv_data))
499 pxa2xx_spi_write(drv_data, SSCR0,
500 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
503 static int null_writer(struct driver_data *drv_data)
505 u8 n_bytes = drv_data->n_bytes;
507 if (pxa2xx_spi_txfifo_full(drv_data)
508 || (drv_data->tx == drv_data->tx_end))
511 pxa2xx_spi_write(drv_data, SSDR, 0);
512 drv_data->tx += n_bytes;
517 static int null_reader(struct driver_data *drv_data)
519 u8 n_bytes = drv_data->n_bytes;
521 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
522 && (drv_data->rx < drv_data->rx_end)) {
523 pxa2xx_spi_read(drv_data, SSDR);
524 drv_data->rx += n_bytes;
527 return drv_data->rx == drv_data->rx_end;
530 static int u8_writer(struct driver_data *drv_data)
532 if (pxa2xx_spi_txfifo_full(drv_data)
533 || (drv_data->tx == drv_data->tx_end))
536 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
537 ++drv_data->tx;
542 static int u8_reader(struct driver_data *drv_data)
544 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
545 && (drv_data->rx < drv_data->rx_end)) {
546 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
547 ++drv_data->rx;
550 return drv_data->rx == drv_data->rx_end;
553 static int u16_writer(struct driver_data *drv_data)
555 if (pxa2xx_spi_txfifo_full(drv_data)
556 || (drv_data->tx == drv_data->tx_end))
559 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
560 drv_data->tx += 2;
565 static int u16_reader(struct driver_data *drv_data)
567 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
568 && (drv_data->rx < drv_data->rx_end)) {
569 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
570 drv_data->rx += 2;
573 return drv_data->rx == drv_data->rx_end;
576 static int u32_writer(struct driver_data *drv_data)
578 if (pxa2xx_spi_txfifo_full(drv_data)
579 || (drv_data->tx == drv_data->tx_end))
582 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
583 drv_data->tx += 4;
588 static int u32_reader(struct driver_data *drv_data)
590 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
591 && (drv_data->rx < drv_data->rx_end)) {
592 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
593 drv_data->rx += 4;
596 return drv_data->rx == drv_data->rx_end;
599 static void reset_sccr1(struct driver_data *drv_data)
602 spi_get_ctldata(drv_data->controller->cur_msg->spi);
605 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
606 switch (drv_data->ssp_type) {
618 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
621 static void int_error_stop(struct driver_data *drv_data, const char* msg)
624 write_SSSR_CS(drv_data, drv_data->clear_sr);
625 reset_sccr1(drv_data);
626 if (!pxa25x_ssp_comp(drv_data))
627 pxa2xx_spi_write(drv_data, SSTO, 0);
628 pxa2xx_spi_flush(drv_data);
629 pxa2xx_spi_off(drv_data);
631 dev_err(&drv_data->pdev->dev, "%s\n", msg);
633 drv_data->controller->cur_msg->status = -EIO;
634 spi_finalize_current_transfer(drv_data->controller);
637 static void int_transfer_complete(struct driver_data *drv_data)
640 write_SSSR_CS(drv_data, drv_data->clear_sr);
641 reset_sccr1(drv_data);
642 if (!pxa25x_ssp_comp(drv_data))
643 pxa2xx_spi_write(drv_data, SSTO, 0);
645 spi_finalize_current_transfer(drv_data->controller);
648 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
650 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
651 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
653 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
656 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
661 int_error_stop(drv_data, "interrupt_transfer: fifo underrun");
666 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
667 if (drv_data->read(drv_data)) {
668 int_transfer_complete(drv_data);
675 if (drv_data->read(drv_data)) {
676 int_transfer_complete(drv_data);
679 } while (drv_data->write(drv_data));
681 if (drv_data->read(drv_data)) {
682 int_transfer_complete(drv_data);
686 if (drv_data->tx == drv_data->tx_end) {
690 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
697 if (pxa25x_ssp_comp(drv_data)) {
700 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
702 bytes_left = drv_data->rx_end - drv_data->rx;
703 switch (drv_data->n_bytes) {
712 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
716 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
718 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
725 static void handle_bad_msg(struct driver_data *drv_data)
727 pxa2xx_spi_off(drv_data);
728 pxa2xx_spi_write(drv_data, SSCR1,
729 pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1);
730 if (!pxa25x_ssp_comp(drv_data))
731 pxa2xx_spi_write(drv_data, SSTO, 0);
732 write_SSSR_CS(drv_data, drv_data->clear_sr);
734 dev_err(&drv_data->pdev->dev,
740 struct driver_data *drv_data = dev_id;
742 u32 mask = drv_data->mask_sr;
751 if (pm_runtime_suspended(&drv_data->pdev->dev))
760 status = pxa2xx_spi_read(drv_data, SSSR);
764 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
777 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
778 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
780 if (!drv_data->controller->cur_msg) {
781 handle_bad_msg(drv_data);
786 return drv_data->transfer_handler(drv_data);
910 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
912 unsigned long ssp_clk = drv_data->controller->max_speed_hz;
913 const struct ssp_device *ssp = drv_data->ssp;
927 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
931 spi_get_ctldata(drv_data->controller->cur_msg->spi);
934 switch (drv_data->ssp_type) {
939 clk_div = ssp_get_clk_div(drv_data, rate);
960 struct driver_data *drv_data = spi_controller_get_devdata(controller);
965 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
993 if (pxa2xx_spi_flush(drv_data) == 0) {
997 drv_data->n_bytes = chip->n_bytes;
998 drv_data->tx = (void *)transfer->tx_buf;
999 drv_data->tx_end = drv_data->tx + transfer->len;
1000 drv_data->rx = transfer->rx_buf;
1001 drv_data->rx_end = drv_data->rx + transfer->len;
1002 drv_data->write = drv_data->tx ? chip->write : null_writer;
1003 drv_data->read = drv_data->rx ? chip->read : null_reader;
1009 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
1012 drv_data->n_bytes = 1;
1013 drv_data->read = drv_data->read != null_reader ?
1015 drv_data->write = drv_data->write != null_writer ?
1018 drv_data->n_bytes = 2;
1019 drv_data->read = drv_data->read != null_reader ?
1021 drv_data->write = drv_data->write != null_writer ?
1024 drv_data->n_bytes = 4;
1025 drv_data->read = drv_data->read != null_reader ?
1027 drv_data->write = drv_data->write != null_writer ?
1049 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1051 err = pxa2xx_spi_dma_prepare(drv_data, transfer);
1056 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1057 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1059 pxa2xx_spi_dma_start(drv_data);
1062 drv_data->transfer_handler = interrupt_transfer;
1065 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1066 write_SSSR_CS(drv_data, drv_data->clear_sr);
1070 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1071 if (!pxa25x_ssp_comp(drv_data))
1082 if (is_lpss_ssp(drv_data)) {
1083 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1085 pxa2xx_spi_write(drv_data, SSIRF,
1087 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1089 pxa2xx_spi_write(drv_data, SSITF,
1093 if (is_quark_x1000_ssp(drv_data) &&
1094 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1095 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1098 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1099 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1102 if (!is_mmp2_ssp(drv_data))
1103 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1104 if (!pxa25x_ssp_comp(drv_data))
1105 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1107 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1109 pxa2xx_spi_write(drv_data, SSCR0, cr0);
1112 if (!pxa25x_ssp_comp(drv_data))
1113 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1116 if (is_mmp2_ssp(drv_data)) {
1117 u8 tx_level = (pxa2xx_spi_read(drv_data, SSSR)
1126 drv_data->tx += tx_level;
1131 while (drv_data->write(drv_data))
1133 if (drv_data->gpiod_ready) {
1134 gpiod_set_value(drv_data->gpiod_ready, 1);
1136 gpiod_set_value(drv_data->gpiod_ready, 0);
1144 pxa2xx_spi_write(drv_data, SSCR1, cr1);
1151 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1154 write_SSSR_CS(drv_data, drv_data->clear_sr);
1155 reset_sccr1(drv_data);
1156 if (!pxa25x_ssp_comp(drv_data))
1157 pxa2xx_spi_write(drv_data, SSTO, 0);
1158 pxa2xx_spi_flush(drv_data);
1159 pxa2xx_spi_off(drv_data);
1161 dev_dbg(&drv_data->pdev->dev, "transfer aborted\n");
1163 drv_data->controller->cur_msg->status = -EINTR;
1164 spi_finalize_current_transfer(drv_data->controller);
1172 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1175 pxa2xx_spi_off(drv_data);
1177 write_SSSR_CS(drv_data, drv_data->clear_sr);
1178 pxa2xx_spi_write(drv_data, SSCR1,
1179 pxa2xx_spi_read(drv_data, SSCR1)
1180 & ~(drv_data->int_cr1 | drv_data->dma_cr1));
1181 if (!pxa25x_ssp_comp(drv_data))
1182 pxa2xx_spi_write(drv_data, SSTO, 0);
1191 if (atomic_read(&drv_data->dma_running))
1192 pxa2xx_spi_dma_stop(drv_data);
1197 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1200 pxa2xx_spi_off(drv_data);
1208 struct driver_data *drv_data =
1216 if (drv_data->cs_gpiods) {
1217 gpiod = drv_data->cs_gpiods[spi->chip_select];
1269 struct driver_data *drv_data =
1274 switch (drv_data->ssp_type) {
1291 config = lpss_get_config(drv_data);
1298 if (spi_controller_is_slave(drv_data->controller)) {
1315 if (drv_data->ssp_type == CE4100_SSP) {
1325 chip->enable_dma = drv_data->controller_info->enable_dma;
1348 if (spi_controller_is_slave(drv_data->controller)) {
1376 switch (drv_data->ssp_type) {
1416 if (drv_data->ssp_type == CE4100_SSP)
1429 struct driver_data *drv_data =
1435 if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods &&
1640 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1642 if (has_acpi_companion(&drv_data->pdev->dev)) {
1643 switch (drv_data->ssp_type) {
1671 struct driver_data *drv_data;
1696 controller = devm_spi_alloc_slave(dev, sizeof(*drv_data));
1698 controller = devm_spi_alloc_master(dev, sizeof(*drv_data));
1705 drv_data = spi_controller_get_devdata(controller);
1706 drv_data->controller = controller;
1707 drv_data->controller_info = platform_info;
1708 drv_data->pdev = pdev;
1709 drv_data->ssp = ssp;
1728 drv_data->ssp_type = ssp->type;
1730 drv_data->ioaddr = ssp->mmio_base;
1731 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1732 if (pxa25x_ssp_comp(drv_data)) {
1733 switch (drv_data->ssp_type) {
1742 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1743 drv_data->dma_cr1 = 0;
1744 drv_data->clear_sr = SSSR_ROR;
1745 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1748 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1749 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1750 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1751 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS
1756 drv_data);
1764 status = pxa2xx_spi_dma_setup(drv_data);
1786 if (!pxa25x_ssp_comp(drv_data))
1789 else if (!is_quark_x1000_ssp(drv_data))
1794 pxa2xx_spi_write(drv_data, SSCR0, 0);
1795 switch (drv_data->ssp_type) {
1799 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1803 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1808 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1810 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1825 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1829 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1833 if (!pxa25x_ssp_comp(drv_data))
1834 pxa2xx_spi_write(drv_data, SSTO, 0);
1836 if (!is_quark_x1000_ssp(drv_data))
1837 pxa2xx_spi_write(drv_data, SSPSP, 0);
1839 if (is_lpss_ssp(drv_data)) {
1840 lpss_ssp_setup(drv_data);
1841 config = lpss_get_config(drv_data);
1843 tmp = __lpss_ssp_read_priv(drv_data,
1861 drv_data->cs_gpiods = devm_kcalloc(&pdev->dev,
1864 if (!drv_data->cs_gpiods) {
1881 drv_data->cs_gpiods[i] = gpiod;
1887 drv_data->gpiod_ready = devm_gpiod_get_optional(dev,
1889 if (IS_ERR(drv_data->gpiod_ready)) {
1890 status = PTR_ERR(drv_data->gpiod_ready);
1901 platform_set_drvdata(pdev, drv_data);
1917 pxa2xx_spi_dma_release(drv_data);
1918 free_irq(ssp->irq, drv_data);
1927 struct driver_data *drv_data = platform_get_drvdata(pdev);
1928 struct ssp_device *ssp = drv_data->ssp;
1932 spi_unregister_controller(drv_data->controller);
1935 pxa2xx_spi_write(drv_data, SSCR0, 0);
1939 if (drv_data->controller_info->enable_dma)
1940 pxa2xx_spi_dma_release(drv_data);
1946 free_irq(ssp->irq, drv_data);
1957 struct driver_data *drv_data = dev_get_drvdata(dev);
1958 struct ssp_device *ssp = drv_data->ssp;
1961 status = spi_controller_suspend(drv_data->controller);
1964 pxa2xx_spi_write(drv_data, SSCR0, 0);
1974 struct driver_data *drv_data = dev_get_drvdata(dev);
1975 struct ssp_device *ssp = drv_data->ssp;
1986 return spi_controller_resume(drv_data->controller);
1993 struct driver_data *drv_data = dev_get_drvdata(dev);
1995 clk_disable_unprepare(drv_data->ssp->clk);
2001 struct driver_data *drv_data = dev_get_drvdata(dev);
2004 status = clk_prepare_enable(drv_data->ssp->clk);