Lines Matching refs:virtbase
338 * @virtbase: the virtual memory where the SSP is mapped
372 void __iomem *virtbase;
459 tmp = readw(SSP_CSR(pl022->virtbase));
464 writew(tmp, SSP_CSR(pl022->virtbase));
532 writew((readw(SSP_CR1(pl022->virtbase)) &
533 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
548 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
549 readw(SSP_DR(pl022->virtbase));
550 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
566 writel(chip->cr0, SSP_CR0(pl022->virtbase));
568 writew(chip->cr0, SSP_CR0(pl022->virtbase));
569 writew(chip->cr1, SSP_CR1(pl022->virtbase));
570 writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
571 writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
572 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
573 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
654 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
655 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
657 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
658 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
660 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
661 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
663 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
664 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
665 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
666 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
691 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
695 readw(SSP_DR(pl022->virtbase));
699 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
703 (u16) readw(SSP_DR(pl022->virtbase));
707 readl(SSP_DR(pl022->virtbase));
720 writew(0x0, SSP_DR(pl022->virtbase));
723 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
726 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
729 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
740 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
744 readw(SSP_DR(pl022->virtbase));
748 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
752 (u16) readw(SSP_DR(pl022->virtbase));
756 readl(SSP_DR(pl022->virtbase));
1269 irq_status = readw(SSP_MIS(pl022->virtbase));
1285 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
1295 SSP_IMSC(pl022->virtbase));
1296 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1297 writew((readw(SSP_CR1(pl022->virtbase)) &
1298 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1310 writew((readw(SSP_IMSC(pl022->virtbase)) &
1312 SSP_IMSC(pl022->virtbase));
1322 SSP_IMSC(pl022->virtbase));
1323 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1443 writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase));
1478 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1479 SSP_CR1(pl022->virtbase));
1480 writew(irqflags, SSP_IMSC(pl022->virtbase));
1489 read_cr0 = readl(SSP_CR0(pl022->virtbase));
1491 read_cr0 = readw(SSP_CR0(pl022->virtbase));
1492 read_cr1 = readw(SSP_CR1(pl022->virtbase));
1493 read_dmacr = readw(SSP_DMACR(pl022->virtbase));
1494 read_sr = readw(SSP_SR(pl022->virtbase));
1545 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1546 SSP_CR1(pl022->virtbase));
1617 writew((readw(SSP_CR1(pl022->virtbase)) &
1618 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
2225 pl022->virtbase = devm_ioremap(dev, adev->res.start,
2227 if (pl022->virtbase == NULL) {
2232 &adev->res.start, pl022->virtbase);
2252 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
2253 SSP_CR1(pl022->virtbase));