Lines Matching refs:pl022
27 #include <linux/amba/pl022.h>
334 * struct pl022 - This is the private SSP driver data structure
368 struct pl022 {
443 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command);
448 * @pl022: SSP driver private data structure
455 static void internal_cs_control(struct pl022 *pl022, u32 command)
459 tmp = readw(SSP_CSR(pl022->virtbase));
461 tmp &= ~BIT(pl022->cur_cs);
463 tmp |= BIT(pl022->cur_cs);
464 writew(tmp, SSP_CSR(pl022->virtbase));
467 static void pl022_cs_control(struct pl022 *pl022, u32 command)
469 if (pl022->vendor->internal_cs_ctrl)
470 internal_cs_control(pl022, command);
471 else if (gpio_is_valid(pl022->cur_cs))
472 gpio_set_value(pl022->cur_cs, command);
474 pl022->cur_chip->cs_control(command);
481 * @pl022: SSP driver private data structure
483 static void giveback(struct pl022 *pl022)
486 pl022->next_msg_cs_active = false;
488 last_transfer = list_last_entry(&pl022->cur_msg->transfers,
512 next_msg = spi_get_next_queued_message(pl022->master);
518 if (next_msg && next_msg->spi != pl022->cur_msg->spi)
520 if (!next_msg || pl022->cur_msg->state == STATE_ERROR)
521 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
523 pl022->next_msg_cs_active = true;
527 pl022->cur_msg = NULL;
528 pl022->cur_transfer = NULL;
529 pl022->cur_chip = NULL;
532 writew((readw(SSP_CR1(pl022->virtbase)) &
533 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
535 spi_finalize_current_message(pl022->master);
540 * @pl022: SSP driver private data structure
542 static int flush(struct pl022 *pl022)
546 dev_dbg(&pl022->adev->dev, "flush\n");
548 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
549 readw(SSP_DR(pl022->virtbase));
550 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
552 pl022->exp_fifo_level = 0;
559 * @pl022: SSP driver private data structure
561 static void restore_state(struct pl022 *pl022)
563 struct chip_data *chip = pl022->cur_chip;
565 if (pl022->vendor->extended_cr)
566 writel(chip->cr0, SSP_CR0(pl022->virtbase));
568 writew(chip->cr0, SSP_CR0(pl022->virtbase));
569 writew(chip->cr1, SSP_CR1(pl022->virtbase));
570 writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
571 writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
572 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
573 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
649 * @pl022: SSP driver private data structure
651 static void load_ssp_default_config(struct pl022 *pl022)
653 if (pl022->vendor->pl023) {
654 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
655 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
656 } else if (pl022->vendor->extended_cr) {
657 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
658 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
660 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
661 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
663 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
664 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
665 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
666 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
671 * set in pl022.
673 static void readwriter(struct pl022 *pl022)
686 dev_dbg(&pl022->adev->dev,
688 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end);
691 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
692 && (pl022->rx < pl022->rx_end)) {
693 switch (pl022->read) {
695 readw(SSP_DR(pl022->virtbase));
698 *(u8 *) (pl022->rx) =
699 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
702 *(u16 *) (pl022->rx) =
703 (u16) readw(SSP_DR(pl022->virtbase));
706 *(u32 *) (pl022->rx) =
707 readl(SSP_DR(pl022->virtbase));
710 pl022->rx += (pl022->cur_chip->n_bytes);
711 pl022->exp_fifo_level--;
716 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth)
717 && (pl022->tx < pl022->tx_end)) {
718 switch (pl022->write) {
720 writew(0x0, SSP_DR(pl022->virtbase));
723 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
726 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
729 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
732 pl022->tx += (pl022->cur_chip->n_bytes);
733 pl022->exp_fifo_level++;
740 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
741 && (pl022->rx < pl022->rx_end)) {
742 switch (pl022->read) {
744 readw(SSP_DR(pl022->virtbase));
747 *(u8 *) (pl022->rx) =
748 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
751 *(u16 *) (pl022->rx) =
752 (u16) readw(SSP_DR(pl022->virtbase));
755 *(u32 *) (pl022->rx) =
756 readl(SSP_DR(pl022->virtbase));
759 pl022->rx += (pl022->cur_chip->n_bytes);
760 pl022->exp_fifo_level--;
771 * @pl022: SSP driver private data structure
778 static void *next_transfer(struct pl022 *pl022)
780 struct spi_message *msg = pl022->cur_msg;
781 struct spi_transfer *trans = pl022->cur_transfer;
785 pl022->cur_transfer =
798 static void unmap_free_dma_scatter(struct pl022 *pl022)
801 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl,
802 pl022->sgt_tx.nents, DMA_TO_DEVICE);
803 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl,
804 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
805 sg_free_table(&pl022->sgt_rx);
806 sg_free_table(&pl022->sgt_tx);
811 struct pl022 *pl022 = data;
812 struct spi_message *msg = pl022->cur_msg;
814 BUG_ON(!pl022->sgt_rx.sgl);
827 dma_sync_sg_for_cpu(&pl022->adev->dev,
828 pl022->sgt_rx.sgl,
829 pl022->sgt_rx.nents,
832 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) {
833 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i);
842 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) {
843 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i);
855 unmap_free_dma_scatter(pl022);
858 msg->actual_length += pl022->cur_transfer->len;
860 msg->state = next_transfer(pl022);
861 if (msg->state != STATE_DONE && pl022->cur_transfer->cs_change)
862 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
863 tasklet_schedule(&pl022->pump_transfers);
866 static void setup_dma_scatter(struct pl022 *pl022,
893 dev_dbg(&pl022->adev->dev,
904 sg_set_page(sg, virt_to_page(pl022->dummypage),
907 dev_dbg(&pl022->adev->dev,
918 * @pl022: SSP driver's private data structure
920 static int configure_dma(struct pl022 *pl022)
923 .src_addr = SSP_DR(pl022->phybase),
928 .dst_addr = SSP_DR(pl022->phybase),
935 struct dma_chan *rxchan = pl022->dma_rx_channel;
936 struct dma_chan *txchan = pl022->dma_tx_channel;
950 switch (pl022->rx_lev_trig) {
967 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1;
971 switch (pl022->tx_lev_trig) {
988 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1;
992 switch (pl022->read) {
1008 switch (pl022->write) {
1035 pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE);
1036 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages);
1038 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC);
1042 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC);
1047 setup_dma_scatter(pl022, pl022->rx,
1048 pl022->cur_transfer->len, &pl022->sgt_rx);
1049 setup_dma_scatter(pl022, pl022->tx,
1050 pl022->cur_transfer->len, &pl022->sgt_tx);
1053 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
1054 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
1058 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl,
1059 pl022->sgt_tx.nents, DMA_TO_DEVICE);
1065 pl022->sgt_rx.sgl,
1073 pl022->sgt_tx.sgl,
1082 rxdesc->callback_param = pl022;
1089 pl022->dma_running = true;
1097 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl,
1098 pl022->sgt_tx.nents, DMA_TO_DEVICE);
1100 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
1101 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
1103 sg_free_table(&pl022->sgt_tx);
1105 sg_free_table(&pl022->sgt_rx);
1110 static int pl022_dma_probe(struct pl022 *pl022)
1121 pl022->dma_rx_channel = dma_request_channel(mask,
1122 pl022->master_info->dma_filter,
1123 pl022->master_info->dma_rx_param);
1124 if (!pl022->dma_rx_channel) {
1125 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n");
1129 pl022->dma_tx_channel = dma_request_channel(mask,
1130 pl022->master_info->dma_filter,
1131 pl022->master_info->dma_tx_param);
1132 if (!pl022->dma_tx_channel) {
1133 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n");
1137 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1138 if (!pl022->dummypage)
1141 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n",
1142 dma_chan_name(pl022->dma_rx_channel),
1143 dma_chan_name(pl022->dma_tx_channel));
1148 dma_release_channel(pl022->dma_tx_channel);
1150 dma_release_channel(pl022->dma_rx_channel);
1151 pl022->dma_rx_channel = NULL;
1153 dev_err(&pl022->adev->dev,
1158 static int pl022_dma_autoprobe(struct pl022 *pl022)
1160 struct device *dev = &pl022->adev->dev;
1171 pl022->dma_rx_channel = chan;
1179 pl022->dma_tx_channel = chan;
1181 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1182 if (!pl022->dummypage) {
1190 dma_release_channel(pl022->dma_tx_channel);
1191 pl022->dma_tx_channel = NULL;
1193 dma_release_channel(pl022->dma_rx_channel);
1194 pl022->dma_rx_channel = NULL;
1199 static void terminate_dma(struct pl022 *pl022)
1201 struct dma_chan *rxchan = pl022->dma_rx_channel;
1202 struct dma_chan *txchan = pl022->dma_tx_channel;
1206 unmap_free_dma_scatter(pl022);
1207 pl022->dma_running = false;
1210 static void pl022_dma_remove(struct pl022 *pl022)
1212 if (pl022->dma_running)
1213 terminate_dma(pl022);
1214 if (pl022->dma_tx_channel)
1215 dma_release_channel(pl022->dma_tx_channel);
1216 if (pl022->dma_rx_channel)
1217 dma_release_channel(pl022->dma_rx_channel);
1218 kfree(pl022->dummypage);
1222 static inline int configure_dma(struct pl022 *pl022)
1227 static inline int pl022_dma_autoprobe(struct pl022 *pl022)
1232 static inline int pl022_dma_probe(struct pl022 *pl022)
1237 static inline void pl022_dma_remove(struct pl022 *pl022)
1257 struct pl022 *pl022 = dev_id;
1258 struct spi_message *msg = pl022->cur_msg;
1262 dev_err(&pl022->adev->dev,
1269 irq_status = readw(SSP_MIS(pl022->virtbase));
1284 dev_err(&pl022->adev->dev, "FIFO overrun\n");
1285 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
1286 dev_err(&pl022->adev->dev,
1295 SSP_IMSC(pl022->virtbase));
1296 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1297 writew((readw(SSP_CR1(pl022->virtbase)) &
1298 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1302 tasklet_schedule(&pl022->pump_transfers);
1306 readwriter(pl022);
1308 if (pl022->tx == pl022->tx_end) {
1310 writew((readw(SSP_IMSC(pl022->virtbase)) &
1312 SSP_IMSC(pl022->virtbase));
1320 if (pl022->rx >= pl022->rx_end) {
1322 SSP_IMSC(pl022->virtbase));
1323 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1324 if (unlikely(pl022->rx > pl022->rx_end)) {
1325 dev_warn(&pl022->adev->dev, "read %u surplus "
1328 (u32) (pl022->rx - pl022->rx_end));
1331 msg->actual_length += pl022->cur_transfer->len;
1333 msg->state = next_transfer(pl022);
1334 if (msg->state != STATE_DONE && pl022->cur_transfer->cs_change)
1335 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
1336 tasklet_schedule(&pl022->pump_transfers);
1347 static int set_up_next_transfer(struct pl022 *pl022,
1353 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes;
1355 dev_err(&pl022->adev->dev,
1358 pl022->cur_transfer->len,
1359 pl022->cur_chip->n_bytes);
1360 dev_err(&pl022->adev->dev, "skipping this message\n");
1363 pl022->tx = (void *)transfer->tx_buf;
1364 pl022->tx_end = pl022->tx + pl022->cur_transfer->len;
1365 pl022->rx = (void *)transfer->rx_buf;
1366 pl022->rx_end = pl022->rx + pl022->cur_transfer->len;
1367 pl022->write =
1368 pl022->tx ? pl022->cur_chip->write : WRITING_NULL;
1369 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL;
1381 struct pl022 *pl022 = (struct pl022 *) data;
1387 message = pl022->cur_msg;
1388 transfer = pl022->cur_transfer;
1393 giveback(pl022);
1400 giveback(pl022);
1417 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1423 if (set_up_next_transfer(pl022, transfer)) {
1426 giveback(pl022);
1430 flush(pl022);
1432 if (pl022->cur_chip->enable_dma) {
1433 if (configure_dma(pl022)) {
1434 dev_dbg(&pl022->adev->dev,
1443 writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase));
1446 static void do_interrupt_dma_transfer(struct pl022 *pl022)
1455 if (!pl022->next_msg_cs_active)
1456 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1458 if (set_up_next_transfer(pl022, pl022->cur_transfer)) {
1460 pl022->cur_msg->state = STATE_ERROR;
1461 pl022->cur_msg->status = -EIO;
1462 giveback(pl022);
1466 if (pl022->cur_chip->enable_dma) {
1468 if (configure_dma(pl022)) {
1469 dev_dbg(&pl022->adev->dev,
1478 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1479 SSP_CR1(pl022->virtbase));
1480 writew(irqflags, SSP_IMSC(pl022->virtbase));
1483 static void print_current_status(struct pl022 *pl022)
1488 if (pl022->vendor->extended_cr)
1489 read_cr0 = readl(SSP_CR0(pl022->virtbase));
1491 read_cr0 = readw(SSP_CR0(pl022->virtbase));
1492 read_cr1 = readw(SSP_CR1(pl022->virtbase));
1493 read_dmacr = readw(SSP_DMACR(pl022->virtbase));
1494 read_sr = readw(SSP_SR(pl022->virtbase));
1496 dev_warn(&pl022->adev->dev, "spi-pl022 CR0: %x\n", read_cr0);
1497 dev_warn(&pl022->adev->dev, "spi-pl022 CR1: %x\n", read_cr1);
1498 dev_warn(&pl022->adev->dev, "spi-pl022 DMACR: %x\n", read_dmacr);
1499 dev_warn(&pl022->adev->dev, "spi-pl022 SR: %x\n", read_sr);
1500 dev_warn(&pl022->adev->dev,
1501 "spi-pl022 exp_fifo_level/fifodepth: %u/%d\n",
1502 pl022->exp_fifo_level,
1503 pl022->vendor->fifodepth);
1507 static void do_polling_transfer(struct pl022 *pl022)
1514 message = pl022->cur_msg;
1520 transfer = pl022->cur_transfer;
1529 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1533 if (!pl022->next_msg_cs_active)
1534 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1538 if (set_up_next_transfer(pl022, transfer)) {
1544 flush(pl022);
1545 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1546 SSP_CR1(pl022->virtbase));
1548 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n");
1551 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) {
1553 readwriter(pl022);
1555 dev_warn(&pl022->adev->dev,
1558 print_current_status(pl022);
1565 message->actual_length += pl022->cur_transfer->len;
1567 message->state = next_transfer(pl022);
1569 && pl022->cur_transfer->cs_change)
1570 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
1581 giveback(pl022);
1588 struct pl022 *pl022 = spi_master_get_devdata(master);
1591 pl022->cur_msg = msg;
1594 pl022->cur_transfer = list_entry(msg->transfers.next,
1598 pl022->cur_chip = spi_get_ctldata(msg->spi);
1599 pl022->cur_cs = pl022->chipselects[msg->spi->chip_select];
1601 restore_state(pl022);
1602 flush(pl022);
1604 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER)
1605 do_polling_transfer(pl022);
1607 do_interrupt_dma_transfer(pl022);
1614 struct pl022 *pl022 = spi_master_get_devdata(master);
1617 writew((readw(SSP_CR1(pl022->virtbase)) &
1618 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1623 static int verify_controller_parameters(struct pl022 *pl022,
1628 dev_err(&pl022->adev->dev,
1633 (!pl022->vendor->unidir)) {
1634 dev_err(&pl022->adev->dev,
1641 dev_err(&pl022->adev->dev,
1648 dev_err(&pl022->adev->dev,
1659 if (pl022->vendor->fifodepth < 16) {
1660 dev_err(&pl022->adev->dev,
1666 if (pl022->vendor->fifodepth < 32) {
1667 dev_err(&pl022->adev->dev,
1673 dev_err(&pl022->adev->dev,
1684 if (pl022->vendor->fifodepth < 16) {
1685 dev_err(&pl022->adev->dev,
1691 if (pl022->vendor->fifodepth < 32) {
1692 dev_err(&pl022->adev->dev,
1698 dev_err(&pl022->adev->dev,
1705 dev_err(&pl022->adev->dev,
1711 dev_err(&pl022->adev->dev,
1716 if (pl022->vendor->extended_cr) {
1721 dev_err(&pl022->adev->dev,
1727 dev_err(&pl022->adev->dev,
1743 static int calculate_effective_freq(struct pl022 *pl022, int freq, struct
1751 rate = clk_get_rate(pl022->clk);
1758 dev_warn(&pl022->adev->dev,
1763 dev_err(&pl022->adev->dev,
1805 WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n",
1810 dev_dbg(&pl022->adev->dev,
1813 dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n",
1855 struct pl022 *pl022 = spi_master_get_devdata(spi->master);
1882 of_property_read_u32(np, "pl022,interface",
1884 of_property_read_u32(np, "pl022,com-mode",
1886 of_property_read_u32(np, "pl022,rx-level-trig",
1888 of_property_read_u32(np, "pl022,tx-level-trig",
1890 of_property_read_u32(np, "pl022,ctrl-len",
1892 of_property_read_u32(np, "pl022,wait-state",
1894 of_property_read_u32(np, "pl022,duplex",
1914 status = calculate_effective_freq(pl022,
1933 status = verify_controller_parameters(pl022, chip_info);
1939 pl022->rx_lev_trig = chip_info->rx_lev_trig;
1940 pl022->tx_lev_trig = chip_info->tx_lev_trig;
1946 if (!gpio_is_valid(pl022->chipselects[spi->chip_select]))
1953 if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) {
1957 pl022->vendor->max_bpw);
1982 && ((pl022->master_info)->enable_dma)) {
2001 if (pl022->vendor->extended_cr) {
2004 if (pl022->vendor->pl023) {
2057 if (pl022->vendor->loopback) {
2113 of_property_read_u32(np, "pl022,autosuspend-delay",
2115 pd->rt = of_property_read_bool(np, "pl022,rt");
2126 struct pl022 *pl022 = NULL; /*Data for this driver */
2148 master = spi_alloc_master(dev, sizeof(struct pl022));
2154 pl022 = spi_master_get_devdata(master);
2155 pl022->master = master;
2156 pl022->master_info = platform_info;
2157 pl022->adev = adev;
2158 pl022->vendor = id->data;
2159 pl022->chipselects = devm_kcalloc(dev, num_cs, sizeof(int),
2161 if (!pl022->chipselects) {
2182 pl022->chipselects[i] = platform_info->chipselects[i];
2183 } else if (pl022->vendor->internal_cs_ctrl) {
2185 pl022->chipselects[i] = i;
2195 pl022->chipselects[i] = cs_gpio;
2198 if (devm_gpio_request(dev, cs_gpio, "ssp-pl022"))
2212 * always MS bit first on the original pl022.
2215 if (pl022->vendor->extended_cr)
2224 pl022->phybase = adev->res.start;
2225 pl022->virtbase = devm_ioremap(dev, adev->res.start,
2227 if (pl022->virtbase == NULL) {
2232 &adev->res.start, pl022->virtbase);
2234 pl022->clk = devm_clk_get(&adev->dev, NULL);
2235 if (IS_ERR(pl022->clk)) {
2236 status = PTR_ERR(pl022->clk);
2241 status = clk_prepare_enable(pl022->clk);
2248 tasklet_init(&pl022->pump_transfers, pump_transfers,
2249 (unsigned long)pl022);
2252 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
2253 SSP_CR1(pl022->virtbase));
2254 load_ssp_default_config(pl022);
2257 0, "pl022", pl022);
2264 status = pl022_dma_autoprobe(pl022);
2274 status = pl022_dma_probe(pl022);
2280 amba_set_drvdata(adev, pl022);
2304 pl022_dma_remove(pl022);
2306 clk_disable_unprepare(pl022->clk);
2321 struct pl022 *pl022 = amba_get_drvdata(adev);
2323 if (!pl022)
2332 load_ssp_default_config(pl022);
2333 if (pl022->master_info->enable_dma)
2334 pl022_dma_remove(pl022);
2336 clk_disable_unprepare(pl022->clk);
2338 tasklet_disable(&pl022->pump_transfers);
2344 struct pl022 *pl022 = dev_get_drvdata(dev);
2347 ret = spi_master_suspend(pl022->master);
2353 spi_master_resume(pl022->master);
2365 struct pl022 *pl022 = dev_get_drvdata(dev);
2373 ret = spi_master_resume(pl022->master);
2384 struct pl022 *pl022 = dev_get_drvdata(dev);
2386 clk_disable_unprepare(pl022->clk);
2394 struct pl022 *pl022 = dev_get_drvdata(dev);
2397 clk_prepare_enable(pl022->clk);
2495 .name = "ssp-pl022",