Lines Matching defs:SSP_WRITE_BITS
43 #define SSP_WRITE_BITS(reg, val, mask, sb) \
1985 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1987 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1992 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1994 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
2006 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,
2010 SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
2012 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
2014 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
2016 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,
2019 SSP_WRITE_BITS(chip->cr0, bits - 1,
2029 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4);
2030 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5);
2031 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,
2033 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
2036 SSP_WRITE_BITS(chip->cr0, bits - 1,
2038 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
2047 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6);
2053 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7);
2055 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8);
2062 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0);
2064 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);
2065 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
2066 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD,