Lines Matching refs:pic32s
123 static inline void pic32_spi_enable(struct pic32_spi *pic32s)
125 writel(CTRL_ON | CTRL_SIDL, &pic32s->regs->ctrl_set);
128 static inline void pic32_spi_disable(struct pic32_spi *pic32s)
130 writel(CTRL_ON | CTRL_SIDL, &pic32s->regs->ctrl_clr);
136 static void pic32_spi_set_clk_rate(struct pic32_spi *pic32s, u32 spi_ck)
141 div = DIV_ROUND_CLOSEST(clk_get_rate(pic32s->clk), 2 * spi_ck) - 1;
143 writel(div & BAUD_MASK, &pic32s->regs->baud);
146 static inline u32 pic32_rx_fifo_level(struct pic32_spi *pic32s)
148 u32 sr = readl(&pic32s->regs->status);
153 static inline u32 pic32_tx_fifo_level(struct pic32_spi *pic32s)
155 u32 sr = readl(&pic32s->regs->status);
161 static u32 pic32_tx_max(struct pic32_spi *pic32s, int n_bytes)
165 tx_left = (pic32s->tx_end - pic32s->tx) / n_bytes;
166 tx_room = pic32s->fifo_n_elm - pic32_tx_fifo_level(pic32s);
170 * though to use (pic32s->fifo_n_byte - rxfl - txfl) as
176 rxtx_gap = ((pic32s->rx_end - pic32s->rx) -
177 (pic32s->tx_end - pic32s->tx)) / n_bytes;
178 return min3(tx_left, tx_room, (u32)(pic32s->fifo_n_elm - rxtx_gap));
182 static u32 pic32_rx_max(struct pic32_spi *pic32s, int n_bytes)
184 u32 rx_left = (pic32s->rx_end - pic32s->rx) / n_bytes;
186 return min_t(u32, rx_left, pic32_rx_fifo_level(pic32s));
190 static void pic32_spi_rx_##__name(struct pic32_spi *pic32s) \
193 u32 mx = pic32_rx_max(pic32s, sizeof(__type)); \
195 v = read##__bwl(&pic32s->regs->buf); \
196 if (pic32s->rx_end - pic32s->len) \
197 *(__type *)(pic32s->rx) = v; \
198 pic32s->rx += sizeof(__type); \
202 static void pic32_spi_tx_##__name(struct pic32_spi *pic32s) \
205 u32 mx = pic32_tx_max(pic32s, sizeof(__type)); \
208 if (pic32s->tx_end - pic32s->len) \
209 v = *(__type *)(pic32s->tx); \
210 write##__bwl(v, &pic32s->regs->buf); \
211 pic32s->tx += sizeof(__type); \
219 static void pic32_err_stop(struct pic32_spi *pic32s, const char *msg)
222 disable_irq_nosync(pic32s->fault_irq);
223 disable_irq_nosync(pic32s->rx_irq);
224 disable_irq_nosync(pic32s->tx_irq);
227 dev_err(&pic32s->master->dev, "%s\n", msg);
228 if (pic32s->master->cur_msg)
229 pic32s->master->cur_msg->status = -EIO;
230 complete(&pic32s->xfer_done);
235 struct pic32_spi *pic32s = dev_id;
238 status = readl(&pic32s->regs->status);
242 writel(STAT_RX_OV, &pic32s->regs->status_clr);
243 writel(STAT_TX_UR, &pic32s->regs->status_clr);
244 pic32_err_stop(pic32s, "err_irq: fifo ov/ur-run\n");
249 pic32_err_stop(pic32s, "err_irq: frame error");
253 if (!pic32s->master->cur_msg) {
254 pic32_err_stop(pic32s, "err_irq: no mesg");
263 struct pic32_spi *pic32s = dev_id;
265 pic32s->rx_fifo(pic32s);
268 if (pic32s->rx_end == pic32s->rx) {
270 disable_irq_nosync(pic32s->fault_irq);
271 disable_irq_nosync(pic32s->rx_irq);
274 complete(&pic32s->xfer_done);
282 struct pic32_spi *pic32s = dev_id;
284 pic32s->tx_fifo(pic32s);
287 if (pic32s->tx_end == pic32s->tx)
288 disable_irq_nosync(pic32s->tx_irq);
295 struct pic32_spi *pic32s = data;
297 complete(&pic32s->xfer_done);
300 static int pic32_spi_dma_transfer(struct pic32_spi *pic32s,
303 struct spi_master *master = pic32s->master;
334 desc_rx->callback_param = pic32s;
357 static int pic32_spi_dma_config(struct pic32_spi *pic32s, u32 dma_width)
360 struct spi_master *master = pic32s->master;
366 cfg.src_addr = pic32s->dma_base + buf_offset;
367 cfg.dst_addr = pic32s->dma_base + buf_offset;
368 cfg.src_maxburst = pic32s->fifo_n_elm / 2; /* fill one-half */
369 cfg.dst_maxburst = pic32s->fifo_n_elm / 2; /* drain one-half */
373 cfg.slave_id = pic32s->tx_irq;
381 cfg.slave_id = pic32s->rx_irq;
390 static int pic32_spi_set_word_size(struct pic32_spi *pic32s, u8 bits_per_word)
397 pic32s->rx_fifo = pic32_spi_rx_byte;
398 pic32s->tx_fifo = pic32_spi_tx_byte;
403 pic32s->rx_fifo = pic32_spi_rx_word;
404 pic32s->tx_fifo = pic32_spi_tx_word;
409 pic32s->rx_fifo = pic32_spi_rx_dword;
410 pic32s->tx_fifo = pic32_spi_tx_dword;
420 pic32s->fifo_n_elm = DIV_ROUND_UP(pic32s->fifo_n_byte,
423 v = readl(&pic32s->regs->ctrl);
426 writel(v, &pic32s->regs->ctrl);
429 if (test_bit(PIC32F_DMA_PREP, &pic32s->flags))
430 pic32_spi_dma_config(pic32s, dmawidth);
437 struct pic32_spi *pic32s = spi_master_get_devdata(master);
439 pic32_spi_enable(pic32s);
447 struct pic32_spi *pic32s = spi_master_get_devdata(master);
452 if (pic32s->bits_per_word != spi->bits_per_word) {
453 pic32_spi_set_word_size(pic32s, spi->bits_per_word);
454 pic32s->bits_per_word = spi->bits_per_word;
458 if (pic32s->speed_hz != spi->max_speed_hz) {
459 pic32_spi_set_clk_rate(pic32s, spi->max_speed_hz);
460 pic32s->speed_hz = spi->max_speed_hz;
464 if (pic32s->mode != spi->mode) {
465 val = readl(&pic32s->regs->ctrl);
479 writel(val, &pic32s->regs->ctrl);
480 pic32s->mode = spi->mode;
490 struct pic32_spi *pic32s = spi_master_get_devdata(master);
494 test_bit(PIC32F_DMA_PREP, &pic32s->flags);
501 struct pic32_spi *pic32s;
506 pic32s = spi_master_get_devdata(master);
510 (transfer->bits_per_word != pic32s->bits_per_word)) {
511 ret = pic32_spi_set_word_size(pic32s, transfer->bits_per_word);
514 pic32s->bits_per_word = transfer->bits_per_word;
518 if (transfer->speed_hz && (transfer->speed_hz != pic32s->speed_hz)) {
519 pic32_spi_set_clk_rate(pic32s, transfer->speed_hz);
520 pic32s->speed_hz = transfer->speed_hz;
523 reinit_completion(&pic32s->xfer_done);
527 ret = pic32_spi_dma_transfer(pic32s, transfer);
537 pic32s->tx = (const void *)transfer->tx_buf;
538 pic32s->rx = (const void *)transfer->rx_buf;
539 pic32s->tx_end = pic32s->tx + transfer->len;
540 pic32s->rx_end = pic32s->rx + transfer->len;
541 pic32s->len = transfer->len;
544 enable_irq(pic32s->fault_irq);
545 enable_irq(pic32s->rx_irq);
546 enable_irq(pic32s->tx_irq);
550 timeout = wait_for_completion_timeout(&pic32s->xfer_done, 2 * HZ);
574 struct pic32_spi *pic32s = spi_master_get_devdata(master);
576 pic32_spi_disable(pic32s);
610 static int pic32_spi_dma_prep(struct pic32_spi *pic32s, struct device *dev)
612 struct spi_master *master = pic32s->master;
637 if (pic32_spi_dma_config(pic32s, DMA_SLAVE_BUSWIDTH_1_BYTE))
641 set_bit(PIC32F_DMA_PREP, &pic32s->flags);
659 static void pic32_spi_dma_unprep(struct pic32_spi *pic32s)
661 if (!test_bit(PIC32F_DMA_PREP, &pic32s->flags))
664 clear_bit(PIC32F_DMA_PREP, &pic32s->flags);
665 if (pic32s->master->dma_rx)
666 dma_release_channel(pic32s->master->dma_rx);
668 if (pic32s->master->dma_tx)
669 dma_release_channel(pic32s->master->dma_tx);
672 static void pic32_spi_hw_init(struct pic32_spi *pic32s)
677 pic32_spi_disable(pic32s);
679 ctrl = readl(&pic32s->regs->ctrl);
682 pic32s->fifo_n_byte = 16;
704 writel(ctrl, &pic32s->regs->ctrl);
708 writel(ctrl, &pic32s->regs->ctrl2_set);
712 struct pic32_spi *pic32s)
718 pic32s->regs = devm_ioremap_resource(&pdev->dev, mem);
719 if (IS_ERR(pic32s->regs))
720 return PTR_ERR(pic32s->regs);
722 pic32s->dma_base = mem->start;
725 pic32s->fault_irq = platform_get_irq_byname(pdev, "fault");
726 if (pic32s->fault_irq < 0)
727 return pic32s->fault_irq;
729 pic32s->rx_irq = platform_get_irq_byname(pdev, "rx");
730 if (pic32s->rx_irq < 0)
731 return pic32s->rx_irq;
733 pic32s->tx_irq = platform_get_irq_byname(pdev, "tx");
734 if (pic32s->tx_irq < 0)
735 return pic32s->tx_irq;
738 pic32s->clk = devm_clk_get(&pdev->dev, "mck0");
739 if (IS_ERR(pic32s->clk)) {
741 ret = PTR_ERR(pic32s->clk);
745 ret = clk_prepare_enable(pic32s->clk);
749 pic32_spi_hw_init(pic32s);
761 struct pic32_spi *pic32s;
764 master = spi_alloc_master(&pdev->dev, sizeof(*pic32s));
768 pic32s = spi_master_get_devdata(master);
769 pic32s->master = master;
771 ret = pic32_spi_hw_probe(pdev, pic32s);
778 master->max_speed_hz = clk_get_rate(pic32s->clk);
791 ret = pic32_spi_dma_prep(pic32s, &pdev->dev);
795 if (test_bit(PIC32F_DMA_PREP, &pic32s->flags))
798 init_completion(&pic32s->xfer_done);
799 pic32s->mode = -1;
802 irq_set_status_flags(pic32s->fault_irq, IRQ_NOAUTOEN);
803 ret = devm_request_irq(&pdev->dev, pic32s->fault_irq,
805 dev_name(&pdev->dev), pic32s);
807 dev_err(&pdev->dev, "request fault-irq %d\n", pic32s->rx_irq);
812 irq_set_status_flags(pic32s->rx_irq, IRQ_NOAUTOEN);
813 ret = devm_request_irq(&pdev->dev, pic32s->rx_irq,
815 dev_name(&pdev->dev), pic32s);
817 dev_err(&pdev->dev, "request rx-irq %d\n", pic32s->rx_irq);
822 irq_set_status_flags(pic32s->tx_irq, IRQ_NOAUTOEN);
823 ret = devm_request_irq(&pdev->dev, pic32s->tx_irq,
825 dev_name(&pdev->dev), pic32s);
827 dev_err(&pdev->dev, "request tx-irq %d\n", pic32s->tx_irq);
838 platform_set_drvdata(pdev, pic32s);
843 pic32_spi_dma_unprep(pic32s);
844 clk_disable_unprepare(pic32s->clk);
852 struct pic32_spi *pic32s;
854 pic32s = platform_get_drvdata(pdev);
855 pic32_spi_disable(pic32s);
856 clk_disable_unprepare(pic32s->clk);
857 pic32_spi_dma_unprep(pic32s);