Lines Matching refs:tclk_hz
132 u32 tclk_hz;
142 tclk_hz = clk_get_rate(orion_spi->clk);
146 * Given the core_clk (tclk_hz) and the target rate (speed) we
156 unsigned divider = DIV_ROUND_UP(tclk_hz, speed);
206 rate = DIV_ROUND_UP(tclk_hz, speed);
598 unsigned long tclk_hz;
657 tclk_hz = clk_get_rate(spi->clk);
669 DIV_ROUND_UP(tclk_hz, devdata->min_divisor));
672 DIV_ROUND_UP(tclk_hz, devdata->min_divisor);
675 master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor);