Lines Matching defs:spi
28 #include <linux/spi/spi.h>
30 #include <linux/platform_data/spi-omap2-mcspi.h>
159 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
162 struct omap2_mcspi_cs *cs = spi->controller_state;
167 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
169 struct omap2_mcspi_cs *cs = spi->controller_state;
174 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
176 struct omap2_mcspi_cs *cs = spi->controller_state;
181 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
183 struct omap2_mcspi_cs *cs = spi->controller_state;
186 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
187 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
200 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
205 l = mcspi_cached_chconf0(spi);
217 mcspi_write_chconf0(spi, l);
220 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
222 struct omap2_mcspi_cs *cs = spi->controller_state;
231 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
233 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
236 static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable)
238 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
245 if (spi->mode & SPI_CS_HIGH)
248 if (spi->controller_state) {
256 l = mcspi_cached_chconf0(spi);
263 mcspi_write_chconf0(spi, l);
292 static void omap2_mcspi_set_fifo(const struct spi_device *spi,
295 struct spi_master *master = spi->master;
296 struct omap2_mcspi_cs *cs = spi->controller_state;
304 chconf = mcspi_cached_chconf0(spi);
331 mcspi_write_chconf0(spi, chconf);
344 mcspi_write_chconf0(spi, chconf);
381 struct spi_device *spi = data;
382 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
383 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
386 omap2_mcspi_set_dma_req(spi, 1, 0);
393 struct spi_device *spi = data;
394 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
395 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
398 omap2_mcspi_set_dma_req(spi, 0, 0);
403 static void omap2_mcspi_tx_dma(struct spi_device *spi,
411 mcspi = spi_master_get_devdata(spi->master);
412 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
422 tx->callback_param = spi;
428 omap2_mcspi_set_dma_req(spi, 0, 1);
432 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
445 struct omap2_mcspi_cs *cs = spi->controller_state;
449 mcspi = spi_master_get_devdata(spi->master);
450 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
462 l = mcspi_cached_chconf0(spi);
499 dev_err(&spi->dev, "sg_split failed\n");
508 tx->callback_param = spi;
515 omap2_mcspi_set_dma_req(spi, 1, 1);
520 omap2_mcspi_set_dma_req(spi, 1, 0);
534 omap2_mcspi_set_enable(spi, 0);
545 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
554 dev_err(&spi->dev, "DMA RX penultimate word empty\n");
556 omap2_mcspi_set_enable(spi, 1);
563 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
571 dev_err(&spi->dev, "DMA RX last word empty\n");
574 omap2_mcspi_set_enable(spi, 1);
579 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
582 struct omap2_mcspi_cs *cs = spi->controller_state;
594 mcspi = spi_master_get_devdata(spi->master);
595 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
627 if (spi_controller_is_slave(spi->master))
628 mcspi_write_reg(spi->master,
631 omap2_mcspi_tx_dma(spi, xfer, cfg);
635 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
643 omap2_mcspi_set_dma_req(spi, 0, 0);
658 dev_err(&spi->dev, "EOW timed out\n");
671 dev_err(&spi->dev, "TXFFE timed out\n");
676 dev_err(&spi->dev, "TXS timed out\n");
681 dev_err(&spi->dev, "EOT timed out\n");
688 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
690 struct omap2_mcspi_cs *cs = spi->controller_state;
703 l = mcspi_cached_chconf0(spi);
726 dev_err(&spi->dev, "TXS timed out\n");
729 dev_vdbg(&spi->dev, "write-%d %02x\n",
736 dev_err(&spi->dev, "RXS timed out\n");
742 omap2_mcspi_set_enable(spi, 0);
744 dev_vdbg(&spi->dev, "read-%d %02x\n",
748 dev_err(&spi->dev,
754 omap2_mcspi_set_enable(spi, 0);
758 dev_vdbg(&spi->dev, "read-%d %02x\n",
773 dev_err(&spi->dev, "TXS timed out\n");
776 dev_vdbg(&spi->dev, "write-%d %04x\n",
783 dev_err(&spi->dev, "RXS timed out\n");
789 omap2_mcspi_set_enable(spi, 0);
791 dev_vdbg(&spi->dev, "read-%d %04x\n",
795 dev_err(&spi->dev,
801 omap2_mcspi_set_enable(spi, 0);
805 dev_vdbg(&spi->dev, "read-%d %04x\n",
820 dev_err(&spi->dev, "TXS timed out\n");
823 dev_vdbg(&spi->dev, "write-%d %08x\n",
830 dev_err(&spi->dev, "RXS timed out\n");
836 omap2_mcspi_set_enable(spi, 0);
838 dev_vdbg(&spi->dev, "read-%d %08x\n",
842 dev_err(&spi->dev,
848 omap2_mcspi_set_enable(spi, 0);
852 dev_vdbg(&spi->dev, "read-%d %08x\n",
862 dev_err(&spi->dev, "TXS timed out\n");
865 dev_err(&spi->dev, "EOT timed out\n");
871 omap2_mcspi_set_enable(spi, 0);
874 omap2_mcspi_set_enable(spi, 1);
890 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
893 struct omap2_mcspi_cs *cs = spi->controller_state;
896 u8 word_len = spi->bits_per_word;
897 u32 speed_hz = spi->max_speed_hz;
899 mcspi = spi_master_get_devdata(spi->master);
922 l = mcspi_cached_chconf0(spi);
942 if (!(spi->mode & SPI_CS_HIGH))
957 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
961 if (spi->mode & SPI_CPOL)
965 if (spi->mode & SPI_CPHA)
970 mcspi_write_chconf0(spi, l);
972 cs->mode = spi->mode;
974 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
976 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
977 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
1035 static void omap2_mcspi_cleanup(struct spi_device *spi)
1039 if (spi->controller_state) {
1041 cs = spi->controller_state;
1048 static int omap2_mcspi_setup(struct spi_device *spi)
1052 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
1054 struct omap2_mcspi_cs *cs = spi->controller_state;
1060 cs->base = mcspi->base + spi->chip_select * 0x14;
1061 cs->phys = mcspi->phys + spi->chip_select * 0x14;
1065 spi->controller_state = cs;
1075 omap2_mcspi_cleanup(spi);
1080 ret = omap2_mcspi_setup_transfer(spi, NULL);
1082 omap2_mcspi_cleanup(spi);
1121 struct spi_device *spi,
1141 mcspi_dma = mcspi->dma_channels + spi->chip_select;
1142 cs = spi->controller_state;
1143 cd = spi->controller_data;
1146 * The slave driver could have changed spi->mode in which case
1152 if (spi->mode != cs->mode)
1155 omap2_mcspi_set_enable(spi, 0);
1157 if (spi->cs_gpiod)
1158 omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH);
1161 (t->speed_hz != spi->max_speed_hz) ||
1162 (t->bits_per_word != spi->bits_per_word)) {
1164 status = omap2_mcspi_setup_transfer(spi, t);
1167 if (t->speed_hz == spi->max_speed_hz &&
1168 t->bits_per_word == spi->bits_per_word)
1176 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1179 chconf = mcspi_cached_chconf0(spi);
1194 mcspi_write_chconf0(spi, chconf);
1201 master->can_dma(master, spi, t))
1202 omap2_mcspi_set_fifo(spi, t, 1);
1204 omap2_mcspi_set_enable(spi, 1);
1213 master->can_dma(master, spi, t))
1214 count = omap2_mcspi_txrx_dma(spi, t);
1216 count = omap2_mcspi_txrx_pio(spi, t);
1224 omap2_mcspi_set_enable(spi, 0);
1227 omap2_mcspi_set_fifo(spi, t, 0);
1233 status = omap2_mcspi_setup_transfer(spi, NULL);
1241 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1244 omap2_mcspi_set_enable(spi, 0);
1246 if (spi->cs_gpiod)
1247 omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH));
1250 omap2_mcspi_set_fifo(spi, t, 0);
1268 if (msg->spi->controller_state == cs)
1283 struct spi_device *spi,
1286 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
1288 &mcspi->dma_channels[spi->chip_select];
1302 static size_t omap2_mcspi_max_xfer_size(struct spi_device *spi)
1304 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
1306 &mcspi->dma_channels[spi->chip_select];
1415 if (of_property_read_bool(node, "spi-slave"))
1422 /* the spi->mode bits understood by this driver: */
1448 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);