Lines Matching defs:fiu
221 struct npcm_fiu_spi *fiu;
245 static void npcm_fiu_set_drd(struct npcm_fiu_spi *fiu,
248 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
252 fiu->drd_op.addr.buswidth = op->addr.buswidth;
253 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
257 fiu->drd_op.dummy.nbytes = op->dummy.nbytes;
258 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
260 fiu->drd_op.cmd.opcode = op->cmd.opcode;
261 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
264 fiu->drd_op.addr.nbytes = op->addr.nbytes;
270 struct npcm_fiu_spi *fiu =
272 struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select];
278 if (fiu->spix_mode) {
282 if (desc->info.op_tmpl.addr.buswidth != fiu->drd_op.addr.buswidth ||
283 desc->info.op_tmpl.dummy.nbytes != fiu->drd_op.dummy.nbytes ||
284 desc->info.op_tmpl.cmd.opcode != fiu->drd_op.cmd.opcode ||
285 desc->info.op_tmpl.addr.nbytes != fiu->drd_op.addr.nbytes)
286 npcm_fiu_set_drd(fiu, &desc->info.op_tmpl);
297 struct npcm_fiu_spi *fiu =
299 struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select];
305 if (fiu->spix_mode)
318 struct npcm_fiu_spi *fiu =
326 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
330 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CMD,
344 regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, addr);
346 regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, 0x0);
350 regmap_write(fiu->regmap, NPCM_FIU_UMA_CFG, uma_cfg);
351 regmap_write_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
354 ret = regmap_read_poll_timeout(fiu->regmap, NPCM_FIU_UMA_CTS, val,
362 regmap_read(fiu->regmap, NPCM_FIU_UMA_DR0 + (i * 4),
374 struct npcm_fiu_spi *fiu =
381 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
386 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CMD,
392 regmap_write(fiu->regmap, NPCM_FIU_UMA_DW0 + (i * 4),
403 regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, op->addr.val);
405 regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, 0x0);
409 regmap_write(fiu->regmap, NPCM_FIU_UMA_CFG, uma_cfg);
411 regmap_write_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
415 return regmap_read_poll_timeout(fiu->regmap, NPCM_FIU_UMA_CTS, val,
423 struct npcm_fiu_spi *fiu =
434 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
438 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
463 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
500 static void npcm_fiux_set_direct_wr(struct npcm_fiu_spi *fiu)
502 regmap_write(fiu->regmap, NPCM_FIU_DWR_CFG,
504 regmap_update_bits(fiu->regmap, NPCM_FIU_DWR_CFG,
507 regmap_update_bits(fiu->regmap, NPCM_FIU_DWR_CFG,
512 static void npcm_fiux_set_direct_rd(struct npcm_fiu_spi *fiu)
516 regmap_write(fiu->regmap, NPCM_FIU_DRD_CFG,
518 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
521 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
528 struct npcm_fiu_spi *fiu =
530 struct npcm_fiu_chip *chip = &fiu->chip[mem->spi->chip_select];
534 dev_dbg(fiu->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
539 if (fiu->spix_mode || op->addr.nbytes > 4)
542 if (fiu->clkrate != chip->clkrate) {
543 ret = clk_set_rate(fiu->clk, chip->clkrate);
545 dev_warn(fiu->dev, "Failed setting %lu frequency, stay at %lu frequency\n",
546 chip->clkrate, fiu->clkrate);
548 fiu->clkrate = chip->clkrate;
588 struct npcm_fiu_spi *fiu =
590 struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select];
593 if (!fiu->res_mem) {
594 dev_warn(fiu->dev, "Reserved memory not defined, direct read disabled\n");
599 if (!fiu->spix_mode &&
607 devm_ioremap(fiu->dev, (fiu->res_mem->start +
608 (fiu->info->max_map_size *
612 dev_warn(fiu->dev, "Error mapping memory region, direct read disabled\n");
618 if (of_device_is_compatible(fiu->dev->of_node, "nuvoton,npcm750-fiu")) {
622 dev_warn(fiu->dev, "Didn't find nuvoton,npcm750-gcr, direct read disabled\n");
632 if (!fiu->spix_mode)
633 npcm_fiu_set_drd(fiu, &desc->info.op_tmpl);
635 npcm_fiux_set_direct_rd(fiu);
638 npcm_fiux_set_direct_wr(fiu);
647 struct npcm_fiu_spi *fiu = spi_controller_get_devdata(ctrl);
650 chip = &fiu->chip[spi->chip_select];
651 chip->fiu = fiu;
655 fiu->clkrate = clk_get_rate(fiu->clk);
668 { .compatible = "nuvoton,npcm750-fiu", .data = &npxm7xx_fiu_data },
678 struct npcm_fiu_spi *fiu;
683 ctrl = devm_spi_alloc_master(dev, sizeof(*fiu));
687 fiu = spi_controller_get_devdata(ctrl);
696 id = of_alias_get_id(dev->of_node, "fiu");
702 fiu->info = &fiu_data_match->npcm_fiu_data_info[id];
704 platform_set_drvdata(pdev, fiu);
705 fiu->dev = dev;
712 fiu->regmap = devm_regmap_init_mmio(dev, regbase,
714 if (IS_ERR(fiu->regmap)) {
716 return PTR_ERR(fiu->regmap);
719 fiu->res_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM,
721 fiu->clk = devm_clk_get(dev, NULL);
722 if (IS_ERR(fiu->clk))
723 return PTR_ERR(fiu->clk);
725 fiu->spix_mode = of_property_read_bool(dev->of_node,
728 platform_set_drvdata(pdev, fiu);
729 clk_prepare_enable(fiu->clk);
736 ctrl->num_chipselect = fiu->info->max_cs;
741 clk_disable_unprepare(fiu->clk);
748 struct npcm_fiu_spi *fiu = platform_get_drvdata(pdev);
750 clk_disable_unprepare(fiu->clk);