Lines Matching refs:ssp
58 struct mxs_ssp ssp;
67 struct mxs_ssp *ssp = &spi->ssp;
76 mxs_ssp_set_clk_rate(ssp, hz);
79 * ssp->clk_rate. Otherwise we would set the rate every transfer
90 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
96 ssp->base + HW_SSP_CTRL1(ssp));
98 writel(0x0, ssp->base + HW_SSP_CMD0);
99 writel(0x0, ssp->base + HW_SSP_CMD1);
127 struct mxs_ssp *ssp = &spi->ssp;
131 reg = readl_relaxed(ssp->base + offset);
154 struct mxs_ssp *ssp = dev_id;
156 dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
158 readl(ssp->base + HW_SSP_CTRL1(ssp)),
159 readl(ssp->base + HW_SSP_STATUS(ssp)));
167 struct mxs_ssp *ssp = &spi->ssp;
191 ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
211 if (ssp->devid == IMX23_SSP) {
233 ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
240 desc = dmaengine_prep_slave_sg(ssp->dmach,
242 (ssp->devid == IMX23_SSP) ? 1 : 4,
246 dev_err(ssp->dev,
252 desc = dmaengine_prep_slave_sg(ssp->dmach,
258 dev_err(ssp->dev,
274 dma_async_issue_pending(ssp->dmach);
278 dev_err(ssp->dev, "DMA transfer timeout\n");
280 dmaengine_terminate_all(ssp->dmach);
289 dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
302 struct mxs_ssp *ssp = &spi->ssp;
305 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
310 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
312 if (ssp->devid == IMX23_SSP) {
314 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
316 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
318 writel(1, ssp->base + HW_SSP_XFER_SIZE);
323 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
326 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
329 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
335 writel(*buf, ssp->base + HW_SSP_DATA(ssp));
338 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
341 if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
345 *buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
364 struct mxs_ssp *ssp = &spi->ssp;
371 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
373 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
398 ssp->base + HW_SSP_CTRL1(ssp) +
411 ssp->base + HW_SSP_CTRL1(ssp) +
427 stmp_reset_block(ssp->base);
444 struct mxs_ssp *ssp = &spi->ssp;
447 clk_disable_unprepare(ssp->clk);
451 int ret2 = clk_prepare_enable(ssp->clk);
465 struct mxs_ssp *ssp = &spi->ssp;
472 ret = clk_prepare_enable(ssp->clk);
533 struct mxs_ssp *ssp;
579 ssp = &spi->ssp;
580 ssp->dev = &pdev->dev;
581 ssp->clk = clk;
582 ssp->base = base;
583 ssp->devid = devid;
588 dev_name(&pdev->dev), ssp);
592 ssp->dmach = dma_request_chan(&pdev->dev, "rx-tx");
593 if (IS_ERR(ssp->dmach)) {
594 dev_err(ssp->dev, "Failed to request DMA\n");
595 ret = PTR_ERR(ssp->dmach);
599 pm_runtime_enable(ssp->dev);
600 if (!pm_runtime_enabled(ssp->dev)) {
601 ret = mxs_spi_runtime_resume(ssp->dev);
603 dev_err(ssp->dev, "runtime resume failed\n");
608 ret = pm_runtime_get_sync(ssp->dev);
610 pm_runtime_put_noidle(ssp->dev);
611 dev_err(ssp->dev, "runtime_get_sync failed\n");
615 clk_set_rate(ssp->clk, clk_freq);
617 ret = stmp_reset_block(ssp->base);
627 pm_runtime_put(ssp->dev);
632 pm_runtime_put(ssp->dev);
634 pm_runtime_disable(ssp->dev);
636 dma_release_channel(ssp->dmach);
646 struct mxs_ssp *ssp;
650 ssp = &spi->ssp;
656 dma_release_channel(ssp->dmach);