Lines Matching refs:mxic
6 // Mason Yang <masonccyang@mxic.com.tw>
7 // zhengxunli <zhengxunli@mxic.com.tw>
177 static int mxic_spi_clk_enable(struct mxic_spi *mxic)
181 ret = clk_prepare_enable(mxic->send_clk);
185 ret = clk_prepare_enable(mxic->send_dly_clk);
192 clk_disable_unprepare(mxic->send_clk);
197 static void mxic_spi_clk_disable(struct mxic_spi *mxic)
199 clk_disable_unprepare(mxic->send_clk);
200 clk_disable_unprepare(mxic->send_dly_clk);
203 static void mxic_spi_set_input_delay_dqs(struct mxic_spi *mxic, u8 idly_code)
209 mxic->regs + IDLY_CODE(0));
214 mxic->regs + IDLY_CODE(1));
217 static int mxic_spi_clk_setup(struct mxic_spi *mxic, unsigned long freq)
221 ret = clk_set_rate(mxic->send_clk, freq);
225 ret = clk_set_rate(mxic->send_dly_clk, freq);
233 mxic_spi_set_input_delay_dqs(mxic, 0xf);
243 ret = clk_set_phase(mxic->send_dly_clk, 9 * freq / 25000000);
250 static int mxic_spi_set_freq(struct mxic_spi *mxic, unsigned long freq)
254 if (mxic->cur_speed_hz == freq)
257 mxic_spi_clk_disable(mxic);
258 ret = mxic_spi_clk_setup(mxic, freq);
262 ret = mxic_spi_clk_enable(mxic);
266 mxic->cur_speed_hz = freq;
271 static void mxic_spi_hw_init(struct mxic_spi *mxic)
273 writel(0, mxic->regs + DATA_STROB);
274 writel(INT_STS_ALL, mxic->regs + INT_STS_EN);
275 writel(0, mxic->regs + HC_EN);
276 writel(0, mxic->regs + LRD_CFG);
277 writel(0, mxic->regs + LRD_CTRL);
280 mxic->regs + HC_CFG);
283 static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf,
300 ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
305 writel(data, mxic->regs + TXD(nbytes % 4));
307 ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
312 ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
318 data = readl(mxic->regs + RXD);
323 WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY);
351 struct mxic_spi *mxic = spi_master_get_devdata(mem->spi->master);
357 ret = mxic_spi_set_freq(mxic, mem->spi->max_speed_hz);
370 mxic->regs + HC_CFG);
371 writel(HC_EN_BIT, mxic->regs + HC_EN);
388 writel(ss_ctrl, mxic->regs + SS_CTRL(mem->spi->chip_select));
390 writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
391 mxic->regs + HC_CFG);
393 ret = mxic_spi_data_xfer(mxic, &opcode, NULL, 1);
400 ret = mxic_spi_data_xfer(mxic, addr, NULL, op->addr.nbytes);
404 ret = mxic_spi_data_xfer(mxic, NULL, NULL, op->dummy.nbytes);
408 ret = mxic_spi_data_xfer(mxic,
416 writel(readl(mxic->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT,
417 mxic->regs + HC_CFG);
418 writel(0, mxic->regs + HC_EN);
430 struct mxic_spi *mxic = spi_master_get_devdata(spi->master);
433 writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_EN,
434 mxic->regs + HC_CFG);
435 writel(HC_EN_BIT, mxic->regs + HC_EN);
436 writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
437 mxic->regs + HC_CFG);
439 writel(readl(mxic->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT,
440 mxic->regs + HC_CFG);
441 writel(0, mxic->regs + HC_EN);
449 struct mxic_spi *mxic = spi_master_get_devdata(master);
461 ret = mxic_spi_set_freq(mxic, t->speed_hz);
479 mxic->regs + SS_CTRL(0));
481 ret = mxic_spi_data_xfer(mxic, t->tx_buf, t->rx_buf, t->len);
493 struct mxic_spi *mxic = spi_master_get_devdata(master);
495 mxic_spi_clk_disable(mxic);
496 clk_disable_unprepare(mxic->ps_clk);
504 struct mxic_spi *mxic = spi_master_get_devdata(master);
507 ret = clk_prepare_enable(mxic->ps_clk);
513 return mxic_spi_clk_enable(mxic);
525 struct mxic_spi *mxic;
534 mxic = spi_master_get_devdata(master);
538 mxic->ps_clk = devm_clk_get(&pdev->dev, "ps_clk");
539 if (IS_ERR(mxic->ps_clk))
540 return PTR_ERR(mxic->ps_clk);
542 mxic->send_clk = devm_clk_get(&pdev->dev, "send_clk");
543 if (IS_ERR(mxic->send_clk))
544 return PTR_ERR(mxic->send_clk);
546 mxic->send_dly_clk = devm_clk_get(&pdev->dev, "send_dly_clk");
547 if (IS_ERR(mxic->send_dly_clk))
548 return PTR_ERR(mxic->send_dly_clk);
551 mxic->regs = devm_ioremap_resource(&pdev->dev, res);
552 if (IS_ERR(mxic->regs))
553 return PTR_ERR(mxic->regs);
568 mxic_spi_hw_init(mxic);
599 .name = "mxic-spi",
606 MODULE_AUTHOR("Mason Yang <masonccyang@mxic.com.tw>");