Lines Matching defs:spifc
91 * @spifc: the Meson SPI device
94 static int meson_spifc_wait_ready(struct meson_spifc *spifc)
100 regmap_read(spifc->regmap, REG_SLAVE, &data);
111 * @spifc: the Meson SPI device
115 static void meson_spifc_drain_buffer(struct meson_spifc *spifc, u8 *buf,
122 regmap_read(spifc->regmap, REG_C0 + i, &data);
137 * @spifc: the Meson SPI device
141 static void meson_spifc_fill_buffer(struct meson_spifc *spifc, const u8 *buf,
153 regmap_write(spifc->regmap, REG_C0 + i, data);
162 * @spifc: the Meson SPI device
165 static void meson_spifc_setup_speed(struct meson_spifc *spifc, u32 speed)
170 parent = clk_get_rate(spifc->clk);
173 dev_dbg(spifc->dev, "parent %lu, speed %u, n %d\n", parent,
181 regmap_write(spifc->regmap, REG_CLOCK, value);
186 * @spifc: the Meson SPI device
194 static int meson_spifc_txrx(struct meson_spifc *spifc,
203 meson_spifc_fill_buffer(spifc, xfer->tx_buf + offset, len);
206 regmap_update_bits(spifc->regmap, REG_USER, USER_UC_MASK,
208 regmap_write(spifc->regmap, REG_USER1,
212 regmap_update_bits(spifc->regmap, REG_USER, USER_DIN_EN_MS,
222 regmap_update_bits(spifc->regmap, REG_USER4, USER4_CS_ACT,
226 regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_TRST_DONE, 0);
228 regmap_update_bits(spifc->regmap, REG_CMD, CMD_USER, CMD_USER);
230 ret = meson_spifc_wait_ready(spifc);
233 meson_spifc_drain_buffer(spifc, xfer->rx_buf + offset, len);
249 struct meson_spifc *spifc = spi_master_get_devdata(master);
252 meson_spifc_setup_speed(spifc, xfer->speed_hz);
254 regmap_update_bits(spifc->regmap, REG_CTRL, CTRL_ENABLE_AHB, 0);
258 ret = meson_spifc_txrx(spifc, xfer, done, len,
264 regmap_update_bits(spifc->regmap, REG_CTRL, CTRL_ENABLE_AHB,
272 * @spifc: the Meson SPI device
274 static void meson_spifc_hw_init(struct meson_spifc *spifc)
277 regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_SW_RST,
280 regmap_update_bits(spifc->regmap, REG_USER, USER_CMP_MODE, 0);
282 regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_OP_MODE, 0);
288 struct meson_spifc *spifc;
299 spifc = spi_master_get_devdata(master);
300 spifc->dev = &pdev->dev;
308 spifc->regmap = devm_regmap_init_mmio(spifc->dev, base,
310 if (IS_ERR(spifc->regmap)) {
311 ret = PTR_ERR(spifc->regmap);
315 spifc->clk = devm_clk_get(spifc->dev, NULL);
316 if (IS_ERR(spifc->clk)) {
317 dev_err(spifc->dev, "missing clock\n");
318 ret = PTR_ERR(spifc->clk);
322 ret = clk_prepare_enable(spifc->clk);
324 dev_err(spifc->dev, "can't prepare clock\n");
328 rate = clk_get_rate(spifc->clk);
338 meson_spifc_hw_init(spifc);
340 pm_runtime_set_active(spifc->dev);
341 pm_runtime_enable(spifc->dev);
343 ret = devm_spi_register_master(spifc->dev, master);
345 dev_err(spifc->dev, "failed to register spi master\n");
351 clk_disable_unprepare(spifc->clk);
352 pm_runtime_disable(spifc->dev);
361 struct meson_spifc *spifc = spi_master_get_devdata(master);
364 clk_disable_unprepare(spifc->clk);
374 struct meson_spifc *spifc = spi_master_get_devdata(master);
382 clk_disable_unprepare(spifc->clk);
390 struct meson_spifc *spifc = spi_master_get_devdata(master);
394 ret = clk_prepare_enable(spifc->clk);
399 meson_spifc_hw_init(spifc);
403 clk_disable_unprepare(spifc->clk);
413 struct meson_spifc *spifc = spi_master_get_devdata(master);
415 clk_disable_unprepare(spifc->clk);
423 struct meson_spifc *spifc = spi_master_get_devdata(master);
425 return clk_prepare_enable(spifc->clk);
437 { .compatible = "amlogic,meson6-spifc", },
438 { .compatible = "amlogic,meson-gxbb-spifc", },
447 .name = "meson-spifc",