Lines Matching refs:spicc
174 static void meson_spicc_oen_enable(struct meson_spicc_device *spicc)
178 if (!spicc->data->has_oen)
181 conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) |
184 writel_relaxed(conf, spicc->base + SPICC_ENH_CTL0);
187 static inline bool meson_spicc_txfull(struct meson_spicc_device *spicc)
190 readl_relaxed(spicc->base + SPICC_STATREG));
193 static inline bool meson_spicc_rxready(struct meson_spicc_device *spicc)
196 readl_relaxed(spicc->base + SPICC_STATREG));
199 static inline u32 meson_spicc_pull_data(struct meson_spicc_device *spicc)
201 unsigned int bytes = spicc->bytes_per_word;
207 byte = *spicc->tx_buf++;
212 spicc->tx_remain--;
216 static inline void meson_spicc_push_data(struct meson_spicc_device *spicc,
219 unsigned int bytes = spicc->bytes_per_word;
225 *spicc->rx_buf++ = byte;
229 spicc->rx_remain--;
232 static inline void meson_spicc_rx(struct meson_spicc_device *spicc)
235 while (spicc->rx_remain &&
236 meson_spicc_rxready(spicc))
237 meson_spicc_push_data(spicc,
238 readl_relaxed(spicc->base + SPICC_RXDATA));
241 static inline void meson_spicc_tx(struct meson_spicc_device *spicc)
244 while (spicc->tx_remain &&
245 !meson_spicc_txfull(spicc))
246 writel_relaxed(meson_spicc_pull_data(spicc),
247 spicc->base + SPICC_TXDATA);
250 static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc)
254 spicc->xfer_remain /
255 spicc->bytes_per_word,
256 spicc->data->fifo_size);
258 spicc->tx_remain = burst_len;
259 spicc->rx_remain = burst_len;
260 spicc->xfer_remain -= burst_len * spicc->bytes_per_word;
266 spicc->base + SPICC_CONREG);
269 meson_spicc_tx(spicc);
274 struct meson_spicc_device *spicc = (void *) data;
276 writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG);
279 meson_spicc_rx(spicc);
281 if (!spicc->xfer_remain) {
283 writel(0, spicc->base + SPICC_INTREG);
285 spi_finalize_current_transfer(spicc->master);
291 meson_spicc_setup_burst(spicc);
294 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
299 static void meson_spicc_auto_io_delay(struct meson_spicc_device *spicc)
305 if (spicc->data->has_enhance_clk_div) {
307 readl_relaxed(spicc->base + SPICC_ENH_CTL0));
312 readl_relaxed(spicc->base + SPICC_CONREG));
319 hz = clk_get_rate(spicc->clk);
334 conf = readl_relaxed(spicc->base + SPICC_TESTREG);
339 writel_relaxed(conf, spicc->base + SPICC_TESTREG);
342 static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc,
348 conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG);
353 (spicc->bytes_per_word << 3) - 1);
357 writel_relaxed(conf, spicc->base + SPICC_CONREG);
359 clk_set_rate(spicc->clk, xfer->speed_hz);
361 meson_spicc_auto_io_delay(spicc);
363 writel_relaxed(0, spicc->base + SPICC_DMAREG);
366 static void meson_spicc_reset_fifo(struct meson_spicc_device *spicc)
368 if (spicc->data->has_oen)
371 spicc->base + SPICC_ENH_CTL0);
374 spicc->base + SPICC_TESTREG);
376 while (meson_spicc_rxready(spicc))
377 readl_relaxed(spicc->base + SPICC_RXDATA);
379 if (spicc->data->has_oen)
381 spicc->base + SPICC_ENH_CTL0);
388 struct meson_spicc_device *spicc = spi_master_get_devdata(master);
391 spicc->xfer = xfer;
394 spicc->tx_buf = (u8 *)xfer->tx_buf;
395 spicc->rx_buf = (u8 *)xfer->rx_buf;
396 spicc->xfer_remain = xfer->len;
399 spicc->bytes_per_word =
400 DIV_ROUND_UP(spicc->xfer->bits_per_word, 8);
402 if (xfer->len % spicc->bytes_per_word)
406 meson_spicc_setup_xfer(spicc, xfer);
408 meson_spicc_reset_fifo(spicc);
411 meson_spicc_setup_burst(spicc);
414 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
417 writel_relaxed(SPICC_TC_EN, spicc->base + SPICC_INTREG);
425 struct meson_spicc_device *spicc = spi_master_get_devdata(master);
427 u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK;
430 spicc->message = message;
467 writel_relaxed(conf, spicc->base + SPICC_CONREG);
470 writel_relaxed(0, spicc->base + SPICC_PERIODREG);
472 writel_bits_relaxed(SPICC_LBC_W1, 0, spicc->base + SPICC_TESTREG);
479 struct meson_spicc_device *spicc = spi_master_get_devdata(master);
480 u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK;
483 writel(0, spicc->base + SPICC_INTREG);
485 device_reset_optional(&spicc->pdev->dev);
488 writel_relaxed(conf, spicc->base + SPICC_CONREG);
538 struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
540 if (!spicc->master->cur_msg)
550 struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
552 if (!spicc->master->cur_msg)
562 struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
564 if (!spicc->master->cur_msg)
576 static int meson_spicc_pow2_clk_init(struct meson_spicc_device *spicc)
578 struct device *dev = &spicc->pdev->dev;
600 if (spicc->data->has_pclk)
601 parent_data[0].hw = __clk_get_hw(spicc->pclk);
603 parent_data[0].hw = __clk_get_hw(spicc->core);
625 spicc->pow2_div.shift = 16,
626 spicc->pow2_div.width = 3,
627 spicc->pow2_div.flags = CLK_DIVIDER_POWER_OF_TWO,
628 spicc->pow2_div.reg = spicc->base + SPICC_CONREG;
629 spicc->pow2_div.hw.init = &init;
631 spicc->clk = devm_clk_register(dev, &spicc->pow2_div.hw);
632 if (WARN_ON(IS_ERR(spicc->clk)))
633 return PTR_ERR(spicc->clk);
638 static int meson_spicc_enh_clk_init(struct meson_spicc_device *spicc)
640 struct device *dev = &spicc->pdev->dev;
664 if (spicc->data->has_pclk)
665 parent_data[0].hw = __clk_get_hw(spicc->pclk);
667 parent_data[0].hw = __clk_get_hw(spicc->core);
691 enh_div->reg = spicc->base + SPICC_ENH_CTL0;
705 parent_data[0].hw = &spicc->pow2_div.hw;
712 mux->reg = spicc->base + SPICC_ENH_CTL0;
715 spicc->clk = devm_clk_register(dev, &mux->hw);
716 if (WARN_ON(IS_ERR(spicc->clk)))
717 return PTR_ERR(spicc->clk);
725 struct meson_spicc_device *spicc;
728 master = spi_alloc_master(&pdev->dev, sizeof(*spicc));
733 spicc = spi_master_get_devdata(master);
734 spicc->master = master;
736 spicc->data = of_device_get_match_data(&pdev->dev);
737 if (!spicc->data) {
743 spicc->pdev = pdev;
744 platform_set_drvdata(pdev, spicc);
746 spicc->base = devm_platform_ioremap_resource(pdev, 0);
747 if (IS_ERR(spicc->base)) {
749 ret = PTR_ERR(spicc->base);
755 spicc->base + SPICC_CONREG);
758 writel_relaxed(0, spicc->base + SPICC_INTREG);
767 0, NULL, spicc);
773 spicc->core = devm_clk_get(&pdev->dev, "core");
774 if (IS_ERR(spicc->core)) {
776 ret = PTR_ERR(spicc->core);
780 if (spicc->data->has_pclk) {
781 spicc->pclk = devm_clk_get(&pdev->dev, "pclk");
782 if (IS_ERR(spicc->pclk)) {
784 ret = PTR_ERR(spicc->pclk);
789 ret = clk_prepare_enable(spicc->core);
795 ret = clk_prepare_enable(spicc->pclk);
811 master->min_speed_hz = spicc->data->min_speed_hz;
812 master->max_speed_hz = spicc->data->max_speed_hz;
820 meson_spicc_oen_enable(spicc);
822 ret = meson_spicc_pow2_clk_init(spicc);
828 if (spicc->data->has_enhance_clk_div) {
829 ret = meson_spicc_enh_clk_init(spicc);
845 clk_disable_unprepare(spicc->pclk);
848 clk_disable_unprepare(spicc->core);
858 struct meson_spicc_device *spicc = platform_get_drvdata(pdev);
861 writel(0, spicc->base + SPICC_CONREG);
863 clk_disable_unprepare(spicc->core);
864 clk_disable_unprepare(spicc->pclk);
866 spi_master_put(spicc->master);
896 .compatible = "amlogic,meson-gx-spicc",
900 .compatible = "amlogic,meson-axg-spicc",
904 .compatible = "amlogic,meson-g12a-spicc",
915 .name = "meson-spicc",