Lines Matching refs:init
580 struct clk_init_data init;
585 memset(&init, 0, sizeof(init));
588 init.parent_data = parent_data;
597 init.name = name;
598 init.ops = &clk_fixed_factor_ops;
599 init.flags = 0;
604 init.num_parents = 1;
608 pow2_fixed_div->hw.init = &init;
615 init.name = name;
616 init.ops = &meson_spicc_pow2_clk_ops;
621 init.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE;
623 init.num_parents = 1;
629 spicc->pow2_div.hw.init = &init;
644 struct clk_init_data init;
649 memset(&init, 0, sizeof(init));
652 init.parent_data = parent_data;
661 init.name = name;
662 init.ops = &clk_fixed_factor_ops;
663 init.flags = 0;
668 init.num_parents = 1;
672 enh_fixed_div->hw.init = &init;
683 init.name = name;
684 init.ops = &clk_divider_ops;
685 init.flags = CLK_SET_RATE_PARENT;
687 init.num_parents = 1;
692 enh_div->hw.init = &init;
703 init.name = name;
704 init.ops = &clk_mux_ops;
707 init.num_parents = 2;
708 init.flags = CLK_SET_RATE_PARENT;
713 mux->hw.init = &init;