Lines Matching defs:spi
19 #include <linux/spi/spi.h>
155 int (*cfg_irq)(struct platform_device *pdev, struct lantiq_ssc_spi *spi);
188 static u32 lantiq_ssc_readl(const struct lantiq_ssc_spi *spi, u32 reg)
190 return __raw_readl(spi->regbase + reg);
193 static void lantiq_ssc_writel(const struct lantiq_ssc_spi *spi, u32 val,
196 __raw_writel(val, spi->regbase + reg);
199 static void lantiq_ssc_maskl(const struct lantiq_ssc_spi *spi, u32 clr,
202 u32 val = __raw_readl(spi->regbase + reg);
206 __raw_writel(val, spi->regbase + reg);
209 static unsigned int tx_fifo_level(const struct lantiq_ssc_spi *spi)
211 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
212 u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT);
217 static unsigned int rx_fifo_level(const struct lantiq_ssc_spi *spi)
219 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
220 u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT);
225 static unsigned int tx_fifo_free(const struct lantiq_ssc_spi *spi)
227 return spi->tx_fifo_size - tx_fifo_level(spi);
230 static void rx_fifo_reset(const struct lantiq_ssc_spi *spi)
232 u32 val = spi->rx_fifo_size << LTQ_SPI_RXFCON_RXFITL_S;
235 lantiq_ssc_writel(spi, val, LTQ_SPI_RXFCON);
238 static void tx_fifo_reset(const struct lantiq_ssc_spi *spi)
243 lantiq_ssc_writel(spi, val, LTQ_SPI_TXFCON);
246 static void rx_fifo_flush(const struct lantiq_ssc_spi *spi)
248 lantiq_ssc_maskl(spi, 0, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON);
251 static void tx_fifo_flush(const struct lantiq_ssc_spi *spi)
253 lantiq_ssc_maskl(spi, 0, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON);
256 static void hw_enter_config_mode(const struct lantiq_ssc_spi *spi)
258 lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE);
261 static void hw_enter_active_mode(const struct lantiq_ssc_spi *spi)
263 lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE);
266 static void hw_setup_speed_hz(const struct lantiq_ssc_spi *spi,
279 spi_clk = clk_get_rate(spi->fpi_clk) / 2;
289 dev_dbg(spi->dev, "spi_clk %u, max_speed_hz %u, brt %u\n",
292 lantiq_ssc_writel(spi, brt, LTQ_SPI_BRT);
295 static void hw_setup_bits_per_word(const struct lantiq_ssc_spi *spi,
303 lantiq_ssc_maskl(spi, LTQ_SPI_CON_BM_M, bm, LTQ_SPI_CON);
306 static void hw_setup_clock_mode(const struct lantiq_ssc_spi *spi,
341 lantiq_ssc_maskl(spi, con_clr, con_set, LTQ_SPI_CON);
344 static void lantiq_ssc_hw_init(const struct lantiq_ssc_spi *spi)
346 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
352 lantiq_ssc_writel(spi, 1 << LTQ_SPI_CLC_RMC_S, LTQ_SPI_CLC);
355 hw_enter_config_mode(spi);
358 lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
361 lantiq_ssc_writel(spi, LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN |
366 hw_setup_bits_per_word(spi, spi->bits_per_word);
367 hw_setup_clock_mode(spi, SPI_MODE_0);
370 lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETMS |
375 lantiq_ssc_writel(spi, 0, LTQ_SPI_GPOCON);
376 lantiq_ssc_writel(spi, 0xFF00, LTQ_SPI_FPGO);
379 rx_fifo_reset(spi);
380 tx_fifo_reset(spi);
383 lantiq_ssc_writel(spi, hwcfg->irnen_t | hwcfg->irnen_r |
390 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
398 dev_dbg(spi->dev, "using internal chipselect %u\n", cs);
400 if (cs < spi->base_cs) {
401 dev_err(spi->dev,
402 "chipselect %i too small (min %i)\n", cs, spi->base_cs);
407 gpocon = 1 << ((cs - spi->base_cs) + LTQ_SPI_GPOCON_ISCSBN_S);
411 gpocon |= 1 << (cs - spi->base_cs);
413 lantiq_ssc_maskl(spi, 0, gpocon, LTQ_SPI_GPOCON);
421 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
423 hw_enter_config_mode(spi);
424 hw_setup_clock_mode(spi, message->spi->mode);
425 hw_enter_active_mode(spi);
430 static void hw_setup_transfer(struct lantiq_ssc_spi *spi,
437 if (bits_per_word != spi->bits_per_word ||
438 speed_hz != spi->speed_hz) {
439 hw_enter_config_mode(spi);
440 hw_setup_speed_hz(spi, speed_hz);
441 hw_setup_bits_per_word(spi, bits_per_word);
442 hw_enter_active_mode(spi);
444 spi->speed_hz = speed_hz;
445 spi->bits_per_word = bits_per_word;
449 con = lantiq_ssc_readl(spi, LTQ_SPI_CON);
460 lantiq_ssc_writel(spi, con, LTQ_SPI_CON);
466 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
468 flush_workqueue(spi->wq);
471 lantiq_ssc_maskl(spi, 0, LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF,
477 static void tx_fifo_write(struct lantiq_ssc_spi *spi)
483 unsigned int tx_free = tx_fifo_free(spi);
485 spi->fdx_tx_level = 0;
486 while (spi->tx_todo && tx_free) {
487 switch (spi->bits_per_word) {
489 tx8 = spi->tx;
491 spi->tx_todo--;
492 spi->tx++;
495 tx16 = (u16 *) spi->tx;
497 spi->tx_todo -= 2;
498 spi->tx += 2;
501 tx32 = (u32 *) spi->tx;
503 spi->tx_todo -= 4;
504 spi->tx += 4;
512 lantiq_ssc_writel(spi, data, LTQ_SPI_TB);
514 spi->fdx_tx_level++;
518 static void rx_fifo_read_full_duplex(struct lantiq_ssc_spi *spi)
524 unsigned int rx_fill = rx_fifo_level(spi);
530 while (rx_fill != spi->fdx_tx_level)
531 rx_fill = rx_fifo_level(spi);
534 data = lantiq_ssc_readl(spi, LTQ_SPI_RB);
536 switch (spi->bits_per_word) {
538 rx8 = spi->rx;
540 spi->rx_todo--;
541 spi->rx++;
544 rx16 = (u16 *) spi->rx;
546 spi->rx_todo -= 2;
547 spi->rx += 2;
550 rx32 = (u32 *) spi->rx;
552 spi->rx_todo -= 4;
553 spi->rx += 4;
564 static void rx_fifo_read_half_duplex(struct lantiq_ssc_spi *spi)
569 unsigned int rx_fill = rx_fifo_level(spi);
579 if (spi->rx_todo < 4) {
580 rxbv = (lantiq_ssc_readl(spi, LTQ_SPI_STAT) &
582 data = lantiq_ssc_readl(spi, LTQ_SPI_RB);
585 rx8 = spi->rx;
591 spi->rx_todo--;
592 spi->rx++;
595 data = lantiq_ssc_readl(spi, LTQ_SPI_RB);
596 rx32 = (u32 *) spi->rx;
599 spi->rx_todo -= 4;
600 spi->rx += 4;
606 static void rx_request(struct lantiq_ssc_spi *spi)
615 rxreq = spi->rx_todo;
616 rxreq_max = spi->rx_fifo_size * 4;
620 lantiq_ssc_writel(spi, rxreq, LTQ_SPI_RXREQ);
625 struct lantiq_ssc_spi *spi = data;
626 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
627 u32 val = lantiq_ssc_readl(spi, hwcfg->irncr);
629 spin_lock(&spi->lock);
631 lantiq_ssc_writel(spi, val, hwcfg->irncr);
633 if (spi->tx) {
634 if (spi->rx && spi->rx_todo)
635 rx_fifo_read_full_duplex(spi);
637 if (spi->tx_todo)
638 tx_fifo_write(spi);
639 else if (!tx_fifo_level(spi))
641 } else if (spi->rx) {
642 if (spi->rx_todo) {
643 rx_fifo_read_half_duplex(spi);
645 if (spi->rx_todo)
646 rx_request(spi);
654 spin_unlock(&spi->lock);
658 queue_work(spi->wq, &spi->work);
659 spin_unlock(&spi->lock);
666 struct lantiq_ssc_spi *spi = data;
667 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
668 u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT);
669 u32 val = lantiq_ssc_readl(spi, hwcfg->irncr);
674 spin_lock(&spi->lock);
676 lantiq_ssc_writel(spi, val, hwcfg->irncr);
679 dev_err(spi->dev, "receive underflow error\n");
681 dev_err(spi->dev, "transmit underflow error\n");
683 dev_err(spi->dev, "abort error\n");
685 dev_err(spi->dev, "receive overflow error\n");
687 dev_err(spi->dev, "transmit overflow error\n");
689 dev_err(spi->dev, "mode error\n");
692 lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
695 if (spi->master->cur_msg)
696 spi->master->cur_msg->status = -EIO;
697 queue_work(spi->wq, &spi->work);
698 spin_unlock(&spi->lock);
705 struct lantiq_ssc_spi *spi = data;
706 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
707 u32 val = lantiq_ssc_readl(spi, hwcfg->irncr);
721 static int transfer_start(struct lantiq_ssc_spi *spi, struct spi_device *spidev,
726 spin_lock_irqsave(&spi->lock, flags);
728 spi->tx = t->tx_buf;
729 spi->rx = t->rx_buf;
732 spi->tx_todo = t->len;
735 tx_fifo_write(spi);
738 if (spi->rx) {
739 spi->rx_todo = t->len;
742 if (!spi->tx)
743 rx_request(spi);
746 spin_unlock_irqrestore(&spi->lock, flags);
760 struct lantiq_ssc_spi *spi;
764 spi = container_of(work, typeof(*spi), work);
766 do_div(timeout, spi->speed_hz);
771 u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT);
774 spi_finalize_current_transfer(spi->master);
781 if (spi->master->cur_msg)
782 spi->master->cur_msg->status = -EIO;
783 spi_finalize_current_transfer(spi->master);
789 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
792 rx_fifo_flush(spi);
793 tx_fifo_flush(spi);
798 struct lantiq_ssc_spi *spi = spi_master_get_devdata(spidev->master);
803 fgpo = (1 << (cs - spi->base_cs));
805 fgpo = (1 << (cs - spi->base_cs + LTQ_SPI_FGPO_SETOUTN_S));
807 lantiq_ssc_writel(spi, fgpo, LTQ_SPI_FPGO);
814 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
816 hw_setup_transfer(spi, spidev, t);
818 return transfer_start(spi, spidev, t);
821 static int intel_lgm_cfg_irq(struct platform_device *pdev, struct lantiq_ssc_spi *spi)
829 return devm_request_irq(&pdev->dev, irq, intel_lgm_ssc_isr, 0, "spi", spi);
832 static int lantiq_cfg_irq(struct platform_device *pdev, struct lantiq_ssc_spi *spi)
841 0, LTQ_SPI_RX_IRQ_NAME, spi);
850 0, LTQ_SPI_TX_IRQ_NAME, spi);
860 0, LTQ_SPI_ERR_IRQ_NAME, spi);
895 { .compatible = "lantiq,ase-spi", .data = &lantiq_ssc_xway, },
896 { .compatible = "lantiq,falcon-spi", .data = &lantiq_ssc_xrx, },
897 { .compatible = "lantiq,xrx100-spi", .data = &lantiq_ssc_xrx, },
898 { .compatible = "intel,lgm-spi", .data = &intel_ssc_lgm, },
907 struct lantiq_ssc_spi *spi;
925 spi = spi_master_get_devdata(master);
926 spi->master = master;
927 spi->dev = dev;
928 spi->hwcfg = hwcfg;
929 platform_set_drvdata(pdev, spi);
930 spi->regbase = devm_platform_ioremap_resource(pdev, 0);
931 if (IS_ERR(spi->regbase)) {
932 err = PTR_ERR(spi->regbase);
936 err = hwcfg->cfg_irq(pdev, spi);
940 spi->spi_clk = devm_clk_get(dev, "gate");
941 if (IS_ERR(spi->spi_clk)) {
942 err = PTR_ERR(spi->spi_clk);
945 err = clk_prepare_enable(spi->spi_clk);
954 spi->fpi_clk = clk_get_fpi();
956 spi->fpi_clk = clk_get(dev, "freq");
958 if (IS_ERR(spi->fpi_clk)) {
959 err = PTR_ERR(spi->fpi_clk);
966 spi->base_cs = 1;
967 of_property_read_u32(pdev->dev.of_node, "base-cs", &spi->base_cs);
969 spin_lock_init(&spi->lock);
970 spi->bits_per_word = 8;
971 spi->speed_hz = 0;
987 spi->wq = alloc_ordered_workqueue(dev_name(dev), WQ_MEM_RECLAIM);
988 if (!spi->wq) {
992 INIT_WORK(&spi->work, lantiq_ssc_bussy_work);
994 id = lantiq_ssc_readl(spi, LTQ_SPI_ID);
995 spi->tx_fifo_size = (id >> LTQ_SPI_ID_TXFS_S) & hwcfg->fifo_size_mask;
996 spi->rx_fifo_size = (id >> LTQ_SPI_ID_RXFS_S) & hwcfg->fifo_size_mask;
1000 lantiq_ssc_hw_init(spi);
1004 revision, spi->tx_fifo_size, spi->rx_fifo_size, supports_dma);
1015 destroy_workqueue(spi->wq);
1017 clk_put(spi->fpi_clk);
1019 clk_disable_unprepare(spi->spi_clk);
1028 struct lantiq_ssc_spi *spi = platform_get_drvdata(pdev);
1030 lantiq_ssc_writel(spi, 0, LTQ_SPI_IRNEN);
1031 lantiq_ssc_writel(spi, 0, LTQ_SPI_CLC);
1032 rx_fifo_flush(spi);
1033 tx_fifo_flush(spi);
1034 hw_enter_config_mode(spi);
1036 destroy_workqueue(spi->wq);
1037 clk_disable_unprepare(spi->spi_clk);
1038 clk_put(spi->fpi_clk);
1047 .name = "spi-lantiq-ssc",
1057 MODULE_ALIAS("platform:spi-lantiq-ssc");