Lines Matching defs:mode
53 #define LTQ_SPI_CLC_SMC_S 16 /* Clock divider for sleep mode */
55 #define LTQ_SPI_CLC_RMC_S 8 /* Clock divider for normal run mode */
70 #define LTQ_SPI_CON_EM BIT(24) /* Echo mode */
108 #define LTQ_SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */
109 #define LTQ_SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */
114 #define LTQ_SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */
115 #define LTQ_SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */
307 unsigned int mode)
312 * SPI mode mapping in CON register:
319 if (mode & SPI_CPHA)
324 if (mode & SPI_CPOL)
330 if (mode & SPI_LSB_FIRST)
335 /* Set loopback mode */
336 if (mode & SPI_LOOP)
349 * Set clock divider for run mode to 1 to
354 /* Put controller into config mode */
365 /* Setup default SPI mode */
369 /* Enable master mode and clear error flags */
406 /* set GPO pin to CS mode */
410 if (spidev->mode & SPI_CS_HIGH)
424 hw_setup_clock_mode(spi, message->spi->mode);
572 * In RX-only mode the bits per word value is ignored by HW. A value
689 dev_err(spi->dev, "mode error\n");
741 /* start shift clock in RX-only mode */
802 if (!!(spidev->mode & SPI_CS_HIGH) == enable)