Lines Matching refs:spfi
104 static inline u32 spfi_readl(struct img_spfi *spfi, u32 reg)
106 return readl(spfi->regs + reg);
109 static inline void spfi_writel(struct img_spfi *spfi, u32 val, u32 reg)
111 writel(val, spfi->regs + reg);
114 static inline void spfi_start(struct img_spfi *spfi)
118 val = spfi_readl(spfi, SPFI_CONTROL);
120 spfi_writel(spfi, val, SPFI_CONTROL);
123 static inline void spfi_reset(struct img_spfi *spfi)
125 spfi_writel(spfi, SPFI_CONTROL_SOFT_RESET, SPFI_CONTROL);
126 spfi_writel(spfi, 0, SPFI_CONTROL);
129 static int spfi_wait_all_done(struct img_spfi *spfi)
134 u32 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
137 spfi_writel(spfi, SPFI_INTERRUPT_ALLDONETRIG,
144 dev_err(spfi->dev, "Timed out waiting for transaction to complete\n");
145 spfi_reset(spfi);
150 static unsigned int spfi_pio_write32(struct img_spfi *spfi, const u32 *buf,
157 spfi_writel(spfi, SPFI_INTERRUPT_SDFUL, SPFI_INTERRUPT_CLEAR);
158 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
161 spfi_writel(spfi, buf[count], SPFI_TX_32BIT_VALID_DATA);
168 static unsigned int spfi_pio_write8(struct img_spfi *spfi, const u8 *buf,
175 spfi_writel(spfi, SPFI_INTERRUPT_SDFUL, SPFI_INTERRUPT_CLEAR);
176 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
179 spfi_writel(spfi, buf[count], SPFI_TX_8BIT_VALID_DATA);
186 static unsigned int spfi_pio_read32(struct img_spfi *spfi, u32 *buf,
193 spfi_writel(spfi, SPFI_INTERRUPT_GDEX32BIT,
195 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
198 buf[count] = spfi_readl(spfi, SPFI_RX_32BIT_VALID_DATA);
205 static unsigned int spfi_pio_read8(struct img_spfi *spfi, u8 *buf,
212 spfi_writel(spfi, SPFI_INTERRUPT_GDEX8BIT,
214 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
217 buf[count] = spfi_readl(spfi, SPFI_RX_8BIT_VALID_DATA);
228 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
240 spfi_start(spfi);
249 tx_count = spfi_pio_write32(spfi, tx_buf, tx_bytes);
251 tx_count = spfi_pio_write8(spfi, tx_buf, tx_bytes);
254 rx_count = spfi_pio_read32(spfi, rx_buf, rx_bytes);
256 rx_count = spfi_pio_read8(spfi, rx_buf, rx_bytes);
267 dev_err(spfi->dev, "PIO transfer timed out\n");
271 ret = spfi_wait_all_done(spfi);
280 struct img_spfi *spfi = data;
283 spfi_wait_all_done(spfi);
285 spin_lock_irqsave(&spfi->lock, flags);
286 spfi->rx_dma_busy = false;
287 if (!spfi->tx_dma_busy)
288 spi_finalize_current_transfer(spfi->master);
289 spin_unlock_irqrestore(&spfi->lock, flags);
294 struct img_spfi *spfi = data;
297 spfi_wait_all_done(spfi);
299 spin_lock_irqsave(&spfi->lock, flags);
300 spfi->tx_dma_busy = false;
301 if (!spfi->rx_dma_busy)
302 spi_finalize_current_transfer(spfi->master);
303 spin_unlock_irqrestore(&spfi->lock, flags);
310 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
314 spfi->rx_dma_busy = false;
315 spfi->tx_dma_busy = false;
320 rxconf.src_addr = spfi->phys + SPFI_RX_32BIT_VALID_DATA;
324 rxconf.src_addr = spfi->phys + SPFI_RX_8BIT_VALID_DATA;
328 dmaengine_slave_config(spfi->rx_ch, &rxconf);
330 rxdesc = dmaengine_prep_slave_sg(spfi->rx_ch, xfer->rx_sg.sgl,
338 rxdesc->callback_param = spfi;
344 txconf.dst_addr = spfi->phys + SPFI_TX_32BIT_VALID_DATA;
348 txconf.dst_addr = spfi->phys + SPFI_TX_8BIT_VALID_DATA;
352 dmaengine_slave_config(spfi->tx_ch, &txconf);
354 txdesc = dmaengine_prep_slave_sg(spfi->tx_ch, xfer->tx_sg.sgl,
362 txdesc->callback_param = spfi;
366 spfi->rx_dma_busy = true;
368 dma_async_issue_pending(spfi->rx_ch);
371 spfi_start(spfi);
374 spfi->tx_dma_busy = true;
376 dma_async_issue_pending(spfi->tx_ch);
382 dmaengine_terminate_all(spfi->rx_ch);
383 dmaengine_terminate_all(spfi->tx_ch);
390 struct img_spfi *spfi = spi_master_get_devdata(master);
397 spin_lock_irqsave(&spfi->lock, flags);
398 if (spfi->tx_dma_busy || spfi->rx_dma_busy) {
399 spfi->tx_dma_busy = false;
400 spfi->rx_dma_busy = false;
402 dmaengine_terminate_all(spfi->tx_ch);
403 dmaengine_terminate_all(spfi->rx_ch);
405 spin_unlock_irqrestore(&spfi->lock, flags);
410 struct img_spfi *spfi = spi_master_get_devdata(master);
413 val = spfi_readl(spfi, SPFI_PORT_STATE);
425 spfi_writel(spfi, val, SPFI_PORT_STATE);
433 struct img_spfi *spfi = spi_master_get_devdata(master);
435 spfi_reset(spfi);
443 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
450 div = DIV_ROUND_UP(clk_get_rate(spfi->spfi_clk), xfer->speed_hz);
453 val = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(spi->chip_select));
457 spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi->chip_select));
459 spfi_writel(spfi, xfer->len << SPFI_TRANSACTION_TSIZE_SHIFT,
462 val = spfi_readl(spfi, SPFI_CONTROL);
476 spfi_writel(spfi, val, SPFI_CONTROL);
483 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
487 dev_err(spfi->dev,
512 struct img_spfi *spfi = (struct img_spfi *)dev_id;
515 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
517 spfi_writel(spfi, SPFI_INTERRUPT_IACCESS, SPFI_INTERRUPT_CLEAR);
518 dev_err(spfi->dev, "Illegal access interrupt");
528 struct img_spfi *spfi;
533 master = spi_alloc_master(&pdev->dev, sizeof(*spfi));
538 spfi = spi_master_get_devdata(master);
539 spfi->dev = &pdev->dev;
540 spfi->master = master;
541 spin_lock_init(&spfi->lock);
544 spfi->regs = devm_ioremap_resource(spfi->dev, res);
545 if (IS_ERR(spfi->regs)) {
546 ret = PTR_ERR(spfi->regs);
549 spfi->phys = res->start;
551 spfi->irq = platform_get_irq(pdev, 0);
552 if (spfi->irq < 0) {
553 ret = spfi->irq;
556 ret = devm_request_irq(spfi->dev, spfi->irq, img_spfi_irq,
557 IRQ_TYPE_LEVEL_HIGH, dev_name(spfi->dev), spfi);
561 spfi->sys_clk = devm_clk_get(spfi->dev, "sys");
562 if (IS_ERR(spfi->sys_clk)) {
563 ret = PTR_ERR(spfi->sys_clk);
566 spfi->spfi_clk = devm_clk_get(spfi->dev, "spfi");
567 if (IS_ERR(spfi->spfi_clk)) {
568 ret = PTR_ERR(spfi->spfi_clk);
572 ret = clk_prepare_enable(spfi->sys_clk);
575 ret = clk_prepare_enable(spfi->spfi_clk);
579 spfi_reset(spfi);
584 spfi_writel(spfi, SPFI_INTERRUPT_IACCESS, SPFI_INTERRUPT_ENABLE);
589 if (of_property_read_bool(spfi->dev->of_node, "img,supports-quad-mode"))
593 master->max_speed_hz = clk_get_rate(spfi->spfi_clk) / 4;
594 master->min_speed_hz = clk_get_rate(spfi->spfi_clk) / 512;
597 * Maximum speed supported by spfi is limited to the lower value
598 * between 1/4 of the SPFI clock or to "spfi-max-frequency"
603 if (!of_property_read_u32(spfi->dev->of_node, "spfi-max-frequency",
615 spfi->tx_ch = dma_request_chan(spfi->dev, "tx");
616 if (IS_ERR(spfi->tx_ch)) {
617 ret = PTR_ERR(spfi->tx_ch);
618 spfi->tx_ch = NULL;
623 spfi->rx_ch = dma_request_chan(spfi->dev, "rx");
624 if (IS_ERR(spfi->rx_ch)) {
625 ret = PTR_ERR(spfi->rx_ch);
626 spfi->rx_ch = NULL;
631 if (!spfi->tx_ch || !spfi->rx_ch) {
632 if (spfi->tx_ch)
633 dma_release_channel(spfi->tx_ch);
634 if (spfi->rx_ch)
635 dma_release_channel(spfi->rx_ch);
636 spfi->tx_ch = NULL;
637 spfi->rx_ch = NULL;
638 dev_warn(spfi->dev, "Failed to get DMA channels, falling back to PIO mode\n");
640 master->dma_tx = spfi->tx_ch;
641 master->dma_rx = spfi->rx_ch;
645 pm_runtime_set_active(spfi->dev);
646 pm_runtime_enable(spfi->dev);
648 ret = devm_spi_register_master(spfi->dev, master);
655 pm_runtime_disable(spfi->dev);
656 if (spfi->rx_ch)
657 dma_release_channel(spfi->rx_ch);
658 if (spfi->tx_ch)
659 dma_release_channel(spfi->tx_ch);
660 clk_disable_unprepare(spfi->spfi_clk);
662 clk_disable_unprepare(spfi->sys_clk);
672 struct img_spfi *spfi = spi_master_get_devdata(master);
674 if (spfi->tx_ch)
675 dma_release_channel(spfi->tx_ch);
676 if (spfi->rx_ch)
677 dma_release_channel(spfi->rx_ch);
679 pm_runtime_disable(spfi->dev);
680 if (!pm_runtime_status_suspended(spfi->dev)) {
681 clk_disable_unprepare(spfi->spfi_clk);
682 clk_disable_unprepare(spfi->sys_clk);
692 struct img_spfi *spfi = spi_master_get_devdata(master);
694 clk_disable_unprepare(spfi->spfi_clk);
695 clk_disable_unprepare(spfi->sys_clk);
703 struct img_spfi *spfi = spi_master_get_devdata(master);
706 ret = clk_prepare_enable(spfi->sys_clk);
709 ret = clk_prepare_enable(spfi->spfi_clk);
711 clk_disable_unprepare(spfi->sys_clk);
730 struct img_spfi *spfi = spi_master_get_devdata(master);
738 spfi_reset(spfi);
752 { .compatible = "img,spfi", },
759 .name = "img-spfi",