Lines Matching refs:se
12 #include <linux/qcom-geni-se.h>
67 struct geni_se se;
98 ret = geni_se_clk_freq_match(&mas->se,
126 struct geni_se *se = &mas->se;
130 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
132 geni_se_cancel_m_cmd(se);
141 geni_se_abort_m_cmd(se);
158 struct geni_se *se = &mas->se;
171 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);
172 m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN);
194 struct geni_se *se = &mas->se;
215 geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0);
217 geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0);
233 struct geni_se *se = &mas->se;
244 geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first,
247 writel(word_len, se->base + SE_SPI_WORD_LEN);
254 struct geni_se *se = &mas->se;
277 writel(clk_sel, se->base + SE_GENI_CLK_SEL);
278 writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG);
281 se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz);
282 ret = geni_icc_set_bw(se);
293 struct geni_se *se = &mas->se;
314 writel(loopback_cfg, se->base + SE_SPI_LOOPBACK);
315 writel(demux_sel, se->base + SE_SPI_DEMUX_SEL);
316 writel(cpha, se->base + SE_SPI_CPHA);
317 writel(cpol, se->base + SE_SPI_CPOL);
318 writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV);
343 struct geni_se *se = &mas->se;
349 proto = geni_se_read_proto(se);
355 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se);
358 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se);
364 geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2);
367 ver = geni_se_get_qup_hw_version(se);
376 geni_se_select_mode(se, GENI_SE_FIFO);
379 spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG);
381 writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG);
403 struct geni_se *se = &mas->se;
411 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
429 iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1);
433 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
441 struct geni_se *se = &mas->se;
449 rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS);
461 readl(se->base + SE_GENI_RX_FIFOn);
476 ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1);
489 struct geni_se *se = &mas->se;
530 writel(len, se->base + SE_SPI_TX_TRANS_LEN);
535 writel(len, se->base + SE_SPI_RX_TRANS_LEN);
544 geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION);
553 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG);
579 struct geni_se *se = &mas->se;
582 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);
617 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
647 writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR);
671 clk = devm_clk_get(dev, "se");
683 mas->se.dev = dev;
684 mas->se.wrapper = dev_get_drvdata(dev->parent);
685 mas->se.base = base;
686 mas->se.clk = clk;
687 mas->se.opp_table = dev_pm_opp_set_clkname(&pdev->dev, "se");
688 if (IS_ERR(mas->se.opp_table))
689 return PTR_ERR(mas->se.opp_table);
717 ret = geni_icc_get(&mas->se, NULL);
721 mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ);
722 mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
724 ret = geni_icc_set_bw(&mas->se);
747 dev_pm_opp_put_clkname(mas->se.opp_table);
762 dev_pm_opp_put_clkname(mas->se.opp_table);
775 ret = geni_se_resources_off(&mas->se);
779 return geni_icc_disable(&mas->se);
788 ret = geni_icc_enable(&mas->se);
792 ret = geni_se_resources_on(&mas->se);