Lines Matching refs:mas
90 struct spi_geni_master *mas,
98 ret = geni_se_clk_freq_match(&mas->se,
99 speed_hz * mas->oversampling,
102 dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n",
107 *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz);
108 actual_hz = sclk_freq / (mas->oversampling * *clk_div);
110 dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz,
112 ret = dev_pm_opp_set_rate(mas->dev, sclk_freq);
114 dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret);
116 mas->cur_sclk_hz = sclk_freq;
124 struct spi_geni_master *mas = spi_master_get_devdata(spi);
126 struct geni_se *se = &mas->se;
128 spin_lock_irq(&mas->lock);
129 reinit_completion(&mas->cancel_done);
131 mas->cur_xfer = NULL;
133 spin_unlock_irq(&mas->lock);
135 time_left = wait_for_completion_timeout(&mas->cancel_done, HZ);
139 spin_lock_irq(&mas->lock);
140 reinit_completion(&mas->abort_done);
142 spin_unlock_irq(&mas->lock);
144 time_left = wait_for_completion_timeout(&mas->abort_done, HZ);
146 dev_err(mas->dev, "Failed to cancel/abort m_cmd\n");
152 mas->abort_failed = true;
156 static bool spi_geni_is_abort_still_pending(struct spi_geni_master *mas)
158 struct geni_se *se = &mas->se;
161 if (!mas->abort_failed)
170 spin_lock_irq(&mas->lock);
173 spin_unlock_irq(&mas->lock);
176 dev_err(mas->dev, "Interrupts pending after abort: %#010x\n",
185 mas->abort_failed = false;
192 struct spi_geni_master *mas = spi_master_get_devdata(slv->master);
193 struct spi_master *spi = dev_get_drvdata(mas->dev);
194 struct geni_se *se = &mas->se;
200 if (set_flag == mas->cs_flag)
203 pm_runtime_get_sync(mas->dev);
205 if (spi_geni_is_abort_still_pending(mas)) {
206 dev_err(mas->dev, "Can't set chip select\n");
210 mas->cs_flag = set_flag;
212 spin_lock_irq(&mas->lock);
213 reinit_completion(&mas->cs_done);
218 spin_unlock_irq(&mas->lock);
220 time_left = wait_for_completion_timeout(&mas->cs_done, HZ);
225 pm_runtime_put(mas->dev);
228 static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode,
233 struct geni_se *se = &mas->se;
240 if (!(mas->fifo_width_bits % bits_per_word))
241 pack_words = mas->fifo_width_bits / bits_per_word;
244 geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first,
250 static int geni_spi_set_clock_and_bw(struct spi_geni_master *mas,
254 struct geni_se *se = &mas->se;
257 if (clk_hz == mas->cur_speed_hz)
260 ret = get_spi_clk_cfg(clk_hz, mas, &idx, &div);
262 dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret);
273 mas->cur_speed_hz = clk_hz;
281 se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz);
292 struct spi_geni_master *mas = spi_master_get_devdata(spi);
293 struct geni_se *se = &mas->se;
297 if (mas->last_mode != spi_slv->mode) {
311 mas->cur_bits_per_word = spi_slv->bits_per_word;
313 spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word);
320 mas->last_mode = spi_slv->mode;
323 return geni_spi_set_clock_and_bw(mas, spi_slv->max_speed_hz);
330 struct spi_geni_master *mas = spi_master_get_devdata(spi);
332 if (spi_geni_is_abort_still_pending(mas))
337 dev_err(mas->dev, "Couldn't select mode %d\n", ret);
341 static int spi_geni_init(struct spi_geni_master *mas)
343 struct geni_se *se = &mas->se;
347 pm_runtime_get_sync(mas->dev);
351 dev_err(mas->dev, "Invalid proto %d\n", proto);
352 pm_runtime_put(mas->dev);
355 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se);
358 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se);
364 geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2);
366 mas->tx_wm = 1;
372 mas->oversampling = 2;
374 mas->oversampling = 1;
383 pm_runtime_put(mas->dev);
387 static unsigned int geni_byte_per_fifo_word(struct spi_geni_master *mas)
394 if (mas->fifo_width_bits % mas->cur_bits_per_word)
395 return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word,
398 return mas->fifo_width_bits / BITS_PER_BYTE;
401 static bool geni_spi_handle_tx(struct spi_geni_master *mas)
403 struct geni_se *se = &mas->se;
406 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);
410 if (!mas->cur_xfer) {
415 max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word;
416 if (mas->tx_rem_bytes < max_bytes)
417 max_bytes = mas->tx_rem_bytes;
419 tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes;
431 mas->tx_rem_bytes -= max_bytes;
432 if (!mas->tx_rem_bytes) {
439 static void geni_spi_handle_rx(struct spi_geni_master *mas)
441 struct geni_se *se = &mas->se;
446 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);
459 if (!mas->cur_xfer) {
465 if (mas->rx_rem_bytes < rx_bytes)
466 rx_bytes = mas->rx_rem_bytes;
468 rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes;
480 mas->rx_rem_bytes -= rx_bytes;
484 struct spi_geni_master *mas,
489 struct geni_se *se = &mas->se;
504 spin_lock_irq(&mas->lock);
505 spin_unlock_irq(&mas->lock);
507 if (xfer->bits_per_word != mas->cur_bits_per_word) {
508 spi_setup_word_len(mas, mode, xfer->bits_per_word);
509 mas->cur_bits_per_word = xfer->bits_per_word;
513 ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz);
517 mas->tx_rem_bytes = 0;
518 mas->rx_rem_bytes = 0;
520 if (!(mas->cur_bits_per_word % MIN_WORD_LEN))
521 len = xfer->len * BITS_PER_BYTE / mas->cur_bits_per_word;
523 len = xfer->len / (mas->cur_bits_per_word / BITS_PER_BYTE + 1);
526 mas->cur_xfer = xfer;
529 mas->tx_rem_bytes = xfer->len;
536 mas->rx_rem_bytes = xfer->len;
543 spin_lock_irq(&mas->lock);
552 if (geni_spi_handle_tx(mas))
553 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG);
555 spin_unlock_irq(&mas->lock);
562 struct spi_geni_master *mas = spi_master_get_devdata(spi);
564 if (spi_geni_is_abort_still_pending(mas))
571 setup_fifo_xfer(xfer, mas, slv->mode, spi);
578 struct spi_geni_master *mas = spi_master_get_devdata(spi);
579 struct geni_se *se = &mas->se;
589 dev_warn(mas->dev, "Unexpected IRQ err status %#010x\n", m_irq);
591 spin_lock(&mas->lock);
594 geni_spi_handle_rx(mas);
597 geni_spi_handle_tx(mas);
600 if (mas->cur_xfer) {
602 mas->cur_xfer = NULL;
616 if (mas->tx_rem_bytes) {
618 dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n",
619 mas->tx_rem_bytes, mas->cur_bits_per_word);
621 if (mas->rx_rem_bytes)
622 dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n",
623 mas->rx_rem_bytes, mas->cur_bits_per_word);
625 complete(&mas->cs_done);
630 complete(&mas->cancel_done);
632 complete(&mas->abort_done);
649 spin_unlock(&mas->lock);
658 struct spi_geni_master *mas;
675 spi = devm_spi_alloc_master(dev, sizeof(*mas));
680 mas = spi_master_get_devdata(spi);
681 mas->irq = irq;
682 mas->dev = dev;
683 mas->se.dev = dev;
684 mas->se.wrapper = dev_get_drvdata(dev->parent);
685 mas->se.base = base;
686 mas->se.clk = clk;
687 mas->se.opp_table = dev_pm_opp_set_clkname(&pdev->dev, "se");
688 if (IS_ERR(mas->se.opp_table))
689 return PTR_ERR(mas->se.opp_table);
709 init_completion(&mas->cs_done);
710 init_completion(&mas->cancel_done);
711 init_completion(&mas->abort_done);
712 spin_lock_init(&mas->lock);
717 ret = geni_icc_get(&mas->se, NULL);
721 mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ);
722 mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
724 ret = geni_icc_set_bw(&mas->se);
728 ret = spi_geni_init(mas);
732 ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi);
742 free_irq(mas->irq, spi);
747 dev_pm_opp_put_clkname(mas->se.opp_table);
754 struct spi_geni_master *mas = spi_master_get_devdata(spi);
759 free_irq(mas->irq, spi);
762 dev_pm_opp_put_clkname(mas->se.opp_table);
769 struct spi_geni_master *mas = spi_master_get_devdata(spi);
775 ret = geni_se_resources_off(&mas->se);
779 return geni_icc_disable(&mas->se);
785 struct spi_geni_master *mas = spi_master_get_devdata(spi);
788 ret = geni_icc_enable(&mas->se);
792 ret = geni_se_resources_on(&mas->se);
796 return dev_pm_opp_set_rate(mas->dev, mas->cur_sclk_hz);