Lines Matching refs:mpc8xxx_spi
91 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
116 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
128 mpc8xxx_spi->rx_shift = cs->rx_shift;
129 mpc8xxx_spi->tx_shift = cs->tx_shift;
130 mpc8xxx_spi->get_rx = cs->get_rx;
131 mpc8xxx_spi->get_tx = cs->get_tx;
176 struct mpc8xxx_spi *mpc8xxx_spi,
193 if (mpc8xxx_spi->set_shifts)
194 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift,
198 mpc8xxx_spi->rx_shift = cs->rx_shift;
199 mpc8xxx_spi->tx_shift = cs->tx_shift;
200 mpc8xxx_spi->get_rx = cs->get_rx;
201 mpc8xxx_spi->get_tx = cs->get_tx;
209 struct mpc8xxx_spi *mpc8xxx_spi;
215 mpc8xxx_spi = spi_master_get_devdata(spi->master);
229 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
231 mpc8xxx_spi,
248 if ((mpc8xxx_spi->spibrg / hz) > 64) {
250 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
253 dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024);
257 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
268 static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
289 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
295 reg_base = mpc8xxx_spi->reg_base;
313 mpc8xxx_spi->tx = t->tx_buf;
314 mpc8xxx_spi->rx = t->rx_buf;
316 reinit_completion(&mpc8xxx_spi->done);
318 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
319 ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
321 ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
325 wait_for_completion(&mpc8xxx_spi->done);
330 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
331 fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
333 return mpc8xxx_spi->count;
339 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
351 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {
372 (mpc8xxx_spi->flags & SPI_CPM1))
436 struct mpc8xxx_spi *mpc8xxx_spi;
453 mpc8xxx_spi = spi_master_get_devdata(spi->master);
455 reg_base = mpc8xxx_spi->reg_base;
494 static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
528 struct mpc8xxx_spi *mspi = context_data;
550 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
551 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
557 } else if (cs < mpc8xxx_spi->native_chipselects) {
568 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
569 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
575 mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts;
578 mpc8xxx_spi->max_bits_per_word = mbits + 1;
580 mpc8xxx_spi->native_chipselects = 0;
582 mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities);
585 master->num_chipselect = mpc8xxx_spi->native_chipselects;
594 struct mpc8xxx_spi *mpc8xxx_spi;
599 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
614 mpc8xxx_spi = spi_master_get_devdata(master);
615 mpc8xxx_spi->max_bits_per_word = 32;
616 mpc8xxx_spi->type = fsl_spi_get_type(dev);
618 ret = fsl_spi_cpm_init(mpc8xxx_spi);
622 mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
623 if (IS_ERR(mpc8xxx_spi->reg_base)) {
624 ret = PTR_ERR(mpc8xxx_spi->reg_base);
628 if (mpc8xxx_spi->type == TYPE_GRLIB)
631 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
639 SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);
641 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
642 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
644 if (mpc8xxx_spi->set_shifts)
646 mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift,
647 &mpc8xxx_spi->tx_shift, 8, 1);
650 ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq,
651 0, "fsl_spi", mpc8xxx_spi);
656 reg_base = mpc8xxx_spi->reg_base;
666 if (mpc8xxx_spi->max_bits_per_word < 8) {
668 regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1);
670 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
680 mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
685 fsl_spi_cpm_free(mpc8xxx_spi);
781 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
783 fsl_spi_cpm_free(mpc8xxx_spi);
828 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
830 fsl_spi_cpm_free(mpc8xxx_spi);
835 MODULE_ALIAS("platform:mpc8xxx_spi");
840 .name = "mpc8xxx_spi",