Lines Matching defs:reg_base

93 	struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
94 __be32 __iomem *mode = &reg_base->mode;
272 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
277 mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
281 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
290 struct fsl_spi_reg __iomem *reg_base;
295 reg_base = mpc8xxx_spi->reg_base;
328 mpc8xxx_spi_write_reg(&reg_base->mask, 0);
437 struct fsl_spi_reg __iomem *reg_base;
455 reg_base = mpc8xxx_spi->reg_base;
458 cs->hw_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
496 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
500 u32 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
509 mpc8xxx_spi_read_reg(&reg_base->event)) &
514 mpc8xxx_spi_write_reg(&reg_base->event, events);
520 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
531 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
534 events = mpc8xxx_spi_read_reg(&reg_base->event);
551 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
558 slvsel = mpc8xxx_spi_read_reg(&reg_base->slvsel);
560 mpc8xxx_spi_write_reg(&reg_base->slvsel, slvsel);
569 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
573 capabilities = mpc8xxx_spi_read_reg(&reg_base->cap);
583 mpc8xxx_spi_write_reg(&reg_base->slvsel, 0xffffffff);
595 struct fsl_spi_reg __iomem *reg_base;
622 mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
623 if (IS_ERR(mpc8xxx_spi->reg_base)) {
624 ret = PTR_ERR(mpc8xxx_spi->reg_base);
656 reg_base = mpc8xxx_spi->reg_base;
659 mpc8xxx_spi_write_reg(&reg_base->mode, 0);
660 mpc8xxx_spi_write_reg(&reg_base->mask, 0);
661 mpc8xxx_spi_write_reg(&reg_base->command, 0);
662 mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
673 mpc8xxx_spi_write_reg(&reg_base->mode, regval);
679 dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,