Lines Matching refs:temp
226 u32 temp;
239 temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
240 temp &= ~TCR_CONTC;
241 writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
257 u32 temp = 0;
259 temp |= fsl_lpspi->config.bpw - 1;
260 temp |= (fsl_lpspi->config.mode & 0x3) << 30;
261 temp |= (fsl_lpspi->config.chip_select & 0x3) << 24;
263 temp |= fsl_lpspi->config.prescale << 27;
270 temp |= TCR_CONT;
272 temp &= ~TCR_CONTC;
274 temp |= TCR_CONTC;
277 writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
279 dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp);
284 u32 temp;
287 temp = fsl_lpspi->watermark >> 1 |
290 temp = fsl_lpspi->watermark >> 1;
292 writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
294 dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp);
380 u32 temp;
392 temp = CFGR1_MASTER;
394 temp = CFGR1_PINCFG;
396 temp |= CFGR1_PCSPOL;
397 writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
399 temp = readl(fsl_lpspi->base + IMX7ULP_CR);
400 temp |= CR_RRF | CR_RTF | CR_MEN;
401 writel(temp, fsl_lpspi->base + IMX7ULP_CR);
403 temp = 0;
405 temp = DER_TDDE | DER_RDDE;
406 writel(temp, fsl_lpspi->base + IMX7ULP_DER);
498 u32 temp;
506 temp = 0x3F << 8;
507 writel(temp, fsl_lpspi->base + IMX7ULP_SR);
510 temp = CR_RRF | CR_RTF;
511 writel(temp, fsl_lpspi->base + IMX7ULP_CR);
822 u32 temp;
902 temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
903 fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
904 fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);