Lines Matching refs:fsl_lpspi
30 #define DRIVER_NAME "fsl_lpspi"
132 static void fsl_lpspi_buf_rx_##type(struct fsl_lpspi_data *fsl_lpspi) \
134 unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \
136 if (fsl_lpspi->rx_buf) { \
137 *(type *)fsl_lpspi->rx_buf = val; \
138 fsl_lpspi->rx_buf += sizeof(type); \
143 static void fsl_lpspi_buf_tx_##type(struct fsl_lpspi_data *fsl_lpspi) \
147 if (fsl_lpspi->tx_buf) { \
148 val = *(type *)fsl_lpspi->tx_buf; \
149 fsl_lpspi->tx_buf += sizeof(type); \
152 fsl_lpspi->remain -= sizeof(type); \
153 writel(val, fsl_lpspi->base + IMX7ULP_TDR); \
163 static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi,
166 writel(enable, fsl_lpspi->base + IMX7ULP_IER);
199 struct fsl_lpspi_data *fsl_lpspi =
203 ret = pm_runtime_resume_and_get(fsl_lpspi->dev);
205 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
214 struct fsl_lpspi_data *fsl_lpspi =
217 pm_runtime_mark_last_busy(fsl_lpspi->dev);
218 pm_runtime_put_autosuspend(fsl_lpspi->dev);
223 static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi)
228 txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
230 while (txfifo_cnt < fsl_lpspi->txfifosize) {
231 if (!fsl_lpspi->remain)
233 fsl_lpspi->tx(fsl_lpspi);
237 if (txfifo_cnt < fsl_lpspi->txfifosize) {
238 if (!fsl_lpspi->is_slave) {
239 temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
241 writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
244 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
246 fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE);
249 static void fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data *fsl_lpspi)
251 while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY))
252 fsl_lpspi->rx(fsl_lpspi);
255 static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi)
259 temp |= fsl_lpspi->config.bpw - 1;
260 temp |= (fsl_lpspi->config.mode & 0x3) << 30;
261 temp |= (fsl_lpspi->config.chip_select & 0x3) << 24;
262 if (!fsl_lpspi->is_slave) {
263 temp |= fsl_lpspi->config.prescale << 27;
269 if (!fsl_lpspi->usedma) {
271 if (fsl_lpspi->is_first_byte)
277 writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
279 dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp);
282 static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi)
286 if (!fsl_lpspi->usedma)
287 temp = fsl_lpspi->watermark >> 1 |
288 (fsl_lpspi->watermark >> 1) << 16;
290 temp = fsl_lpspi->watermark >> 1;
292 writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
294 dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp);
297 static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
299 struct lpspi_config config = fsl_lpspi->config;
303 perclk_rate = clk_get_rate(fsl_lpspi->clk_per);
306 dev_err(fsl_lpspi->dev,
314 fsl_lpspi->config.prescale = prescale;
323 fsl_lpspi->base + IMX7ULP_CCR);
325 dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale=%d, scldiv=%d\n",
336 struct fsl_lpspi_data *fsl_lpspi =
339 switch (fsl_lpspi_bytes_per_word(fsl_lpspi->config.bpw)) {
354 tx.dst_addr = fsl_lpspi->base_phys + IMX7ULP_TDR;
359 dev_err(fsl_lpspi->dev, "TX dma configuration failed with %d\n",
365 rx.src_addr = fsl_lpspi->base_phys + IMX7ULP_RDR;
370 dev_err(fsl_lpspi->dev, "RX dma configuration failed with %d\n",
378 static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
383 if (!fsl_lpspi->is_slave) {
384 ret = fsl_lpspi_set_bitrate(fsl_lpspi);
389 fsl_lpspi_set_watermark(fsl_lpspi);
391 if (!fsl_lpspi->is_slave)
395 if (fsl_lpspi->config.mode & SPI_CS_HIGH)
397 writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
399 temp = readl(fsl_lpspi->base + IMX7ULP_CR);
401 writel(temp, fsl_lpspi->base + IMX7ULP_CR);
404 if (fsl_lpspi->usedma)
406 writel(temp, fsl_lpspi->base + IMX7ULP_DER);
415 struct fsl_lpspi_data *fsl_lpspi =
421 fsl_lpspi->config.mode = spi->mode;
422 fsl_lpspi->config.bpw = t->bits_per_word;
423 fsl_lpspi->config.speed_hz = t->speed_hz;
424 if (fsl_lpspi->is_only_cs1)
425 fsl_lpspi->config.chip_select = 1;
427 fsl_lpspi->config.chip_select = spi->chip_select;
429 if (!fsl_lpspi->config.speed_hz)
430 fsl_lpspi->config.speed_hz = spi->max_speed_hz;
431 if (!fsl_lpspi->config.bpw)
432 fsl_lpspi->config.bpw = spi->bits_per_word;
435 if (fsl_lpspi->config.bpw <= 8) {
436 fsl_lpspi->rx = fsl_lpspi_buf_rx_u8;
437 fsl_lpspi->tx = fsl_lpspi_buf_tx_u8;
438 } else if (fsl_lpspi->config.bpw <= 16) {
439 fsl_lpspi->rx = fsl_lpspi_buf_rx_u16;
440 fsl_lpspi->tx = fsl_lpspi_buf_tx_u16;
442 fsl_lpspi->rx = fsl_lpspi_buf_rx_u32;
443 fsl_lpspi->tx = fsl_lpspi_buf_tx_u32;
446 if (t->len <= fsl_lpspi->txfifosize)
447 fsl_lpspi->watermark = t->len;
449 fsl_lpspi->watermark = fsl_lpspi->txfifosize;
452 fsl_lpspi->usedma = true;
454 fsl_lpspi->usedma = false;
456 return fsl_lpspi_config(fsl_lpspi);
461 struct fsl_lpspi_data *fsl_lpspi =
464 fsl_lpspi->slave_aborted = true;
465 if (!fsl_lpspi->usedma)
466 complete(&fsl_lpspi->xfer_done);
468 complete(&fsl_lpspi->dma_tx_completion);
469 complete(&fsl_lpspi->dma_rx_completion);
477 struct fsl_lpspi_data *fsl_lpspi =
480 if (fsl_lpspi->is_slave) {
481 if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) ||
482 fsl_lpspi->slave_aborted) {
483 dev_dbg(fsl_lpspi->dev, "interrupted\n");
487 if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) {
488 dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n");
496 static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
500 if (!fsl_lpspi->usedma) {
502 fsl_lpspi_intctrl(fsl_lpspi, 0);
507 writel(temp, fsl_lpspi->base + IMX7ULP_SR);
511 writel(temp, fsl_lpspi->base + IMX7ULP_CR);
518 struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
520 complete(&fsl_lpspi->dma_rx_completion);
525 struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
527 complete(&fsl_lpspi->dma_tx_completion);
530 static int fsl_lpspi_calculate_timeout(struct fsl_lpspi_data *fsl_lpspi,
536 timeout = (8 + 4) * size / fsl_lpspi->config.speed_hz;
546 struct fsl_lpspi_data *fsl_lpspi,
566 desc_rx->callback_param = (void *)fsl_lpspi;
568 reinit_completion(&fsl_lpspi->dma_rx_completion);
580 desc_tx->callback_param = (void *)fsl_lpspi;
582 reinit_completion(&fsl_lpspi->dma_tx_completion);
585 fsl_lpspi->slave_aborted = false;
587 if (!fsl_lpspi->is_slave) {
588 transfer_timeout = fsl_lpspi_calculate_timeout(fsl_lpspi,
592 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_tx_completion,
595 dev_err(fsl_lpspi->dev, "I/O Error in DMA TX\n");
598 fsl_lpspi_reset(fsl_lpspi);
602 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_rx_completion,
605 dev_err(fsl_lpspi->dev, "I/O Error in DMA RX\n");
608 fsl_lpspi_reset(fsl_lpspi);
612 if (wait_for_completion_interruptible(&fsl_lpspi->dma_tx_completion) ||
613 fsl_lpspi->slave_aborted) {
614 dev_dbg(fsl_lpspi->dev,
618 fsl_lpspi_reset(fsl_lpspi);
622 if (wait_for_completion_interruptible(&fsl_lpspi->dma_rx_completion) ||
623 fsl_lpspi->slave_aborted) {
624 dev_dbg(fsl_lpspi->dev,
628 fsl_lpspi_reset(fsl_lpspi);
633 fsl_lpspi_reset(fsl_lpspi);
652 struct fsl_lpspi_data *fsl_lpspi,
675 init_completion(&fsl_lpspi->dma_rx_completion);
676 init_completion(&fsl_lpspi->dma_tx_completion);
689 struct fsl_lpspi_data *fsl_lpspi =
693 fsl_lpspi->tx_buf = t->tx_buf;
694 fsl_lpspi->rx_buf = t->rx_buf;
695 fsl_lpspi->remain = t->len;
697 reinit_completion(&fsl_lpspi->xfer_done);
698 fsl_lpspi->slave_aborted = false;
700 fsl_lpspi_write_tx_fifo(fsl_lpspi);
706 fsl_lpspi_reset(fsl_lpspi);
715 struct fsl_lpspi_data *fsl_lpspi =
719 fsl_lpspi->is_first_byte = true;
724 fsl_lpspi_set_cmd(fsl_lpspi);
725 fsl_lpspi->is_first_byte = false;
727 if (fsl_lpspi->usedma)
728 ret = fsl_lpspi_dma_transfer(controller, fsl_lpspi, t);
740 struct fsl_lpspi_data *fsl_lpspi = dev_id;
742 temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER);
743 fsl_lpspi_intctrl(fsl_lpspi, 0);
744 temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR);
746 fsl_lpspi_read_rx_fifo(fsl_lpspi);
749 fsl_lpspi_write_tx_fifo(fsl_lpspi);
754 readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_TXCOUNT) {
755 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
756 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
761 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
762 complete(&fsl_lpspi->xfer_done);
773 struct fsl_lpspi_data *fsl_lpspi;
776 fsl_lpspi = spi_controller_get_devdata(controller);
778 ret = clk_prepare_enable(fsl_lpspi->clk_per);
782 ret = clk_prepare_enable(fsl_lpspi->clk_ipg);
784 clk_disable_unprepare(fsl_lpspi->clk_per);
794 struct fsl_lpspi_data *fsl_lpspi;
796 fsl_lpspi = spi_controller_get_devdata(controller);
798 clk_disable_unprepare(fsl_lpspi->clk_per);
799 clk_disable_unprepare(fsl_lpspi->clk_ipg);
805 static int fsl_lpspi_init_rpm(struct fsl_lpspi_data *fsl_lpspi)
807 struct device *dev = fsl_lpspi->dev;
818 struct fsl_lpspi_data *fsl_lpspi;
838 fsl_lpspi = spi_controller_get_devdata(controller);
839 fsl_lpspi->dev = &pdev->dev;
840 fsl_lpspi->is_slave = is_slave;
841 fsl_lpspi->is_only_cs1 = of_property_read_bool((&pdev->dev)->of_node,
853 if (!fsl_lpspi->is_slave)
856 init_completion(&fsl_lpspi->xfer_done);
859 fsl_lpspi->base = devm_ioremap_resource(&pdev->dev, res);
860 if (IS_ERR(fsl_lpspi->base)) {
861 ret = PTR_ERR(fsl_lpspi->base);
864 fsl_lpspi->base_phys = res->start;
873 dev_name(&pdev->dev), fsl_lpspi);
879 fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per");
880 if (IS_ERR(fsl_lpspi->clk_per)) {
881 ret = PTR_ERR(fsl_lpspi->clk_per);
885 fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
886 if (IS_ERR(fsl_lpspi->clk_ipg)) {
887 ret = PTR_ERR(fsl_lpspi->clk_ipg);
892 ret = fsl_lpspi_init_rpm(fsl_lpspi);
896 ret = pm_runtime_get_sync(fsl_lpspi->dev);
898 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
902 temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
903 fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
904 fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
906 ret = fsl_lpspi_dma_init(&pdev->dev, fsl_lpspi, controller);
924 pm_runtime_mark_last_busy(fsl_lpspi->dev);
925 pm_runtime_put_autosuspend(fsl_lpspi->dev);
930 pm_runtime_dont_use_autosuspend(fsl_lpspi->dev);
931 pm_runtime_put_sync(fsl_lpspi->dev);
932 pm_runtime_disable(fsl_lpspi->dev);
942 struct fsl_lpspi_data *fsl_lpspi =
945 pm_runtime_disable(fsl_lpspi->dev);