Lines Matching defs:espi
116 static inline u32 fsl_espi_read_reg(struct fsl_espi *espi, int offset)
118 return ioread32be(espi->reg_base + offset);
121 static inline u16 fsl_espi_read_reg16(struct fsl_espi *espi, int offset)
123 return ioread16be(espi->reg_base + offset);
126 static inline u8 fsl_espi_read_reg8(struct fsl_espi *espi, int offset)
128 return ioread8(espi->reg_base + offset);
131 static inline void fsl_espi_write_reg(struct fsl_espi *espi, int offset,
134 iowrite32be(val, espi->reg_base + offset);
137 static inline void fsl_espi_write_reg16(struct fsl_espi *espi, int offset,
140 iowrite16be(val, espi->reg_base + offset);
143 static inline void fsl_espi_write_reg8(struct fsl_espi *espi, int offset,
146 iowrite8(val, espi->reg_base + offset);
151 struct fsl_espi *espi = spi_master_get_devdata(m->spi->master);
155 dev_err(espi->dev, "message too long, size is %u bytes\n",
166 dev_err(espi->dev, "bits_per_word/speed_hz should be the same for all transfers\n");
174 dev_err(espi->dev,
214 static void fsl_espi_fill_tx_fifo(struct fsl_espi *espi, u32 events)
223 tx_left = espi->tx_t->len - espi->tx_pos;
224 tx_buf = espi->tx_t->tx_buf;
228 fsl_espi_write_reg(espi, ESPI_SPITF, 0);
229 else if (espi->swab)
230 fsl_espi_write_reg(espi, ESPI_SPITF,
231 swahb32p(tx_buf + espi->tx_pos));
233 fsl_espi_write_reg(espi, ESPI_SPITF,
234 *(u32 *)(tx_buf + espi->tx_pos));
235 espi->tx_pos += 4;
238 } else if (tx_left >= 2 && tx_buf && espi->swab) {
239 fsl_espi_write_reg16(espi, ESPI_SPITF,
240 swab16p(tx_buf + espi->tx_pos));
241 espi->tx_pos += 2;
246 fsl_espi_write_reg8(espi, ESPI_SPITF, 0);
248 fsl_espi_write_reg8(espi, ESPI_SPITF,
249 *(u8 *)(tx_buf + espi->tx_pos));
250 espi->tx_pos += 1;
258 if (list_is_last(&espi->tx_t->transfer_list,
259 espi->m_transfers) || espi->rxskip) {
260 espi->tx_done = true;
263 espi->tx_t = list_next_entry(espi->tx_t, transfer_list);
264 espi->tx_pos = 0;
271 static void fsl_espi_read_rx_fifo(struct fsl_espi *espi, u32 events)
278 rx_left = espi->rx_t->len - espi->rx_pos;
279 rx_buf = espi->rx_t->rx_buf;
282 u32 val = fsl_espi_read_reg(espi, ESPI_SPIRF);
284 if (rx_buf && espi->swab)
285 *(u32 *)(rx_buf + espi->rx_pos) = swahb32(val);
287 *(u32 *)(rx_buf + espi->rx_pos) = val;
288 espi->rx_pos += 4;
291 } else if (rx_left >= 2 && rx_buf && espi->swab) {
292 u16 val = fsl_espi_read_reg16(espi, ESPI_SPIRF);
294 *(u16 *)(rx_buf + espi->rx_pos) = swab16(val);
295 espi->rx_pos += 2;
299 u8 val = fsl_espi_read_reg8(espi, ESPI_SPIRF);
302 *(u8 *)(rx_buf + espi->rx_pos) = val;
303 espi->rx_pos += 1;
310 if (list_is_last(&espi->rx_t->transfer_list,
311 espi->m_transfers)) {
312 espi->rx_done = true;
315 espi->rx_t = list_next_entry(espi->rx_t, transfer_list);
316 espi->rx_pos = 0;
326 struct fsl_espi *espi = spi_master_get_devdata(spi->master);
337 pm = DIV_ROUND_UP(espi->spibrg, hz * 4) - 1;
341 pm = DIV_ROUND_UP(espi->spibrg, hz * 16 * 4) - 1;
348 fsl_espi_write_reg(espi, ESPI_SPMODEx(spi->chip_select),
354 struct fsl_espi *espi = spi_master_get_devdata(spi->master);
359 reinit_completion(&espi->done);
366 if (espi->rxskip) {
367 spcom |= SPCOM_RXSKIP(espi->rxskip);
368 rx_len = t->len - espi->rxskip;
373 fsl_espi_write_reg(espi, ESPI_SPCOM, spcom);
379 fsl_espi_write_reg(espi, ESPI_SPIM, mask);
382 spin_lock_irq(&espi->lock);
383 fsl_espi_fill_tx_fifo(espi, 0);
384 spin_unlock_irq(&espi->lock);
387 ret = wait_for_completion_timeout(&espi->done, 2 * HZ);
389 dev_err(espi->dev, "Transfer timed out!\n");
392 fsl_espi_write_reg(espi, ESPI_SPIM, 0);
399 struct fsl_espi *espi = spi_master_get_devdata(m->spi->master);
404 espi->swab = spi->mode & SPI_LSB_FIRST && trans->bits_per_word > 8;
406 espi->m_transfers = &m->transfers;
407 espi->tx_t = list_first_entry(&m->transfers, struct spi_transfer,
409 espi->tx_pos = 0;
410 espi->tx_done = false;
411 espi->rx_t = list_first_entry(&m->transfers, struct spi_transfer,
413 espi->rx_pos = 0;
414 espi->rx_done = false;
416 espi->rxskip = fsl_espi_check_rxskip_mode(m);
417 if (trans->rx_nbits == SPI_NBITS_DUAL && !espi->rxskip) {
418 dev_err(espi->dev, "Dual output mode requires RXSKIP mode!\n");
423 if (espi->rxskip)
424 espi->rx_t = list_next_entry(espi->rx_t, transfer_list);
487 struct fsl_espi *espi;
498 espi = spi_master_get_devdata(spi->master);
500 pm_runtime_get_sync(espi->dev);
502 cs->hw_mode = fsl_espi_read_reg(espi, ESPI_SPMODEx(spi->chip_select));
515 loop_mode = fsl_espi_read_reg(espi, ESPI_SPMODE);
519 fsl_espi_write_reg(espi, ESPI_SPMODE, loop_mode);
523 pm_runtime_mark_last_busy(espi->dev);
524 pm_runtime_put_autosuspend(espi->dev);
537 static void fsl_espi_cpu_irq(struct fsl_espi *espi, u32 events)
539 if (!espi->rx_done)
540 fsl_espi_read_rx_fifo(espi, events);
542 if (!espi->tx_done)
543 fsl_espi_fill_tx_fifo(espi, events);
545 if (!espi->tx_done || !espi->rx_done)
549 events = fsl_espi_read_reg(espi, ESPI_SPIE);
552 dev_err(espi->dev,
556 dev_err(espi->dev, "Transfer done but rx/tx fifo's aren't empty!\n");
557 dev_err(espi->dev, "SPIE_RXCNT = %d, SPIE_TXCNT = %d\n",
561 complete(&espi->done);
566 struct fsl_espi *espi = context_data;
569 spin_lock(&espi->lock);
572 events = fsl_espi_read_reg(espi, ESPI_SPIE);
573 mask = fsl_espi_read_reg(espi, ESPI_SPIM);
575 spin_unlock(&espi->lock);
579 dev_vdbg(espi->dev, "%s: events %x\n", __func__, events);
581 fsl_espi_cpu_irq(espi, events);
584 fsl_espi_write_reg(espi, ESPI_SPIE, events);
586 spin_unlock(&espi->lock);
595 struct fsl_espi *espi = spi_master_get_devdata(master);
598 regval = fsl_espi_read_reg(espi, ESPI_SPMODE);
600 fsl_espi_write_reg(espi, ESPI_SPMODE, regval);
608 struct fsl_espi *espi = spi_master_get_devdata(master);
611 regval = fsl_espi_read_reg(espi, ESPI_SPMODE);
613 fsl_espi_write_reg(espi, ESPI_SPMODE, regval);
627 struct fsl_espi *espi = spi_master_get_devdata(master);
633 fsl_espi_write_reg(espi, ESPI_SPMODE, 0);
634 fsl_espi_write_reg(espi, ESPI_SPIM, 0);
635 fsl_espi_write_reg(espi, ESPI_SPCOM, 0);
636 fsl_espi_write_reg(espi, ESPI_SPIE, 0xffffffff);
661 fsl_espi_write_reg(espi, ESPI_SPMODEx(cs), csmode);
668 fsl_espi_write_reg(espi, ESPI_SPMODE, SPMODE_INIT_VAL | SPMODE_ENABLE);
675 struct fsl_espi *espi;
695 espi = spi_master_get_devdata(master);
696 spin_lock_init(&espi->lock);
698 espi->dev = dev;
699 espi->spibrg = fsl_get_sys_freq();
700 if (espi->spibrg == -1) {
706 master->min_speed_hz = DIV_ROUND_UP(espi->spibrg, 4 * 16 * 16);
707 master->max_speed_hz = DIV_ROUND_UP(espi->spibrg, 4);
709 init_completion(&espi->done);
711 espi->reg_base = devm_ioremap_resource(dev, mem);
712 if (IS_ERR(espi->reg_base)) {
713 ret = PTR_ERR(espi->reg_base);
718 ret = devm_request_irq(dev, irq, fsl_espi_irq, 0, "fsl_espi", espi);
756 ret = of_property_read_u32(np, "fsl,espi-num-chipselects", &num_cs);
758 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
835 { .compatible = "fsl,mpc8536-espi" },