Lines Matching refs:ctx
108 static int fsi_spi_check_status(struct fsi_spi *ctx)
114 rc = fsi_device_read(ctx->fsi, FSI2SPI_STATUS, &sts_be,
121 dev_err(ctx->dev, "Error with FSI2SPI interface: %08x.\n", sts);
128 static int fsi_spi_read_reg(struct fsi_spi *ctx, u32 offset, u64 *value)
133 u32 cmd = offset + ctx->base;
141 rc = fsi_device_write(ctx->fsi, FSI2SPI_CMD, &cmd_be, sizeof(cmd_be));
145 rc = fsi_spi_check_status(ctx);
149 rc = fsi_device_read(ctx->fsi, FSI2SPI_DATA0, &data_be,
156 rc = fsi_device_read(ctx->fsi, FSI2SPI_DATA1, &data_be,
162 dev_dbg(ctx->dev, "Read %02x[%016llx].\n", offset, *value);
167 static int fsi_spi_write_reg(struct fsi_spi *ctx, u32 offset, u64 value)
172 u32 cmd = offset + ctx->base;
177 dev_dbg(ctx->dev, "Write %02x[%016llx].\n", offset, value);
180 rc = fsi_device_write(ctx->fsi, FSI2SPI_DATA0, &data_be,
186 rc = fsi_device_write(ctx->fsi, FSI2SPI_DATA1, &data_be,
192 rc = fsi_device_write(ctx->fsi, FSI2SPI_CMD, &cmd_be, sizeof(cmd_be));
196 return fsi_spi_check_status(ctx);
225 static int fsi_spi_reset(struct fsi_spi *ctx)
229 dev_dbg(ctx->dev, "Resetting SPI controller.\n");
231 rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,
236 rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,
241 return fsi_spi_write_reg(ctx, SPI_FSI_STATUS, 0ULL);
264 static int fsi_spi_sequence_transfer(struct fsi_spi *ctx,
295 if (ctx->restricted) {
305 dev_warn(ctx->dev, "No sequencer slots; aborting.\n");
323 rc = fsi_spi_write_reg(ctx, SPI_FSI_COUNTER_CFG, cfg);
327 fsi_spi_write_reg(ctx, SPI_FSI_COUNTER_CFG, 0ULL);
336 static int fsi_spi_transfer_data(struct fsi_spi *ctx,
353 rc = fsi_spi_write_reg(ctx, SPI_FSI_DATA_TX, out);
358 rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS,
364 rc = fsi_spi_reset(ctx);
379 rc = fsi_spi_read_reg(ctx, SPI_FSI_COUNTER_CFG, &cfg);
384 rc = fsi_spi_write_reg(ctx, SPI_FSI_DATA_TX, 0);
391 rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS,
397 rc = fsi_spi_reset(ctx);
405 rc = fsi_spi_read_reg(ctx, SPI_FSI_DATA_RX, &in);
417 static int fsi_spi_transfer_init(struct fsi_spi *ctx)
434 rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS, &status);
446 rc = fsi_spi_reset(ctx);
455 rc = fsi_spi_read_reg(ctx, SPI_FSI_CLOCK_CFG, &clock_cfg);
464 rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,
476 struct fsi_spi *ctx = spi_controller_get_devdata(ctlr);
478 rc = fsi_spi_check_mux(ctx->fsi, ctx->dev);
488 transfer->len > (ctx->max_xfr_size + 8)) {
493 dev_dbg(ctx->dev, "Start tx of %d bytes.\n", transfer->len);
495 rc = fsi_spi_transfer_init(ctx);
502 rc = fsi_spi_sequence_transfer(ctx, &seq, transfer);
512 if (next->len > ctx->max_xfr_size) {
517 dev_dbg(ctx->dev, "Sequence rx of %d bytes.\n",
520 rc = fsi_spi_sequence_transfer(ctx, &seq,
531 rc = fsi_spi_write_reg(ctx, SPI_FSI_SEQUENCE, seq.data);
535 rc = fsi_spi_transfer_data(ctx, transfer);
540 rc = fsi_spi_transfer_data(ctx, next);
557 struct fsi_spi *ctx = spi_controller_get_devdata(spi->controller);
559 return ctx->max_xfr_size;
575 struct fsi_spi *ctx;
581 ctlr = spi_alloc_master(dev, sizeof(*ctx));
591 ctx = spi_controller_get_devdata(ctlr);
592 ctx->dev = &ctlr->dev;
593 ctx->fsi = fsi;
594 ctx->base = base + SPI_FSI_BASE;
597 ctx->restricted = true;
598 ctx->max_xfr_size = SPI_FSI_MAX_XFR_SIZE_RESTRICTED;
600 ctx->restricted = false;
601 ctx->max_xfr_size = SPI_FSI_MAX_XFR_SIZE;