Lines Matching refs:cr0
28 u32 cr0;
268 u32 cr0 = 0;
272 cr0 |= SSI_MOTO_SPI << SPI_FRF_OFFSET;
279 cr0 |= ((spi->mode & SPI_CPOL) ? 1 : 0) << SPI_SCOL_OFFSET;
280 cr0 |= ((spi->mode & SPI_CPHA) ? 1 : 0) << SPI_SCPH_OFFSET;
283 cr0 |= ((spi->mode & SPI_LOOP) ? 1 : 0) << SPI_SRL_OFFSET;
286 cr0 |= SSI_MOTO_SPI << DWC_SSI_CTRLR0_FRF_OFFSET;
293 cr0 |= ((spi->mode & SPI_CPOL) ? 1 : 0) << DWC_SSI_CTRLR0_SCPOL_OFFSET;
294 cr0 |= ((spi->mode & SPI_CPHA) ? 1 : 0) << DWC_SSI_CTRLR0_SCPH_OFFSET;
297 cr0 |= ((spi->mode & SPI_LOOP) ? 1 : 0) << DWC_SSI_CTRLR0_SRL_OFFSET;
300 cr0 |= DWC_SSI_CTRLR0_KEEMBAY_MST;
303 return cr0;
310 u32 cr0 = chip->cr0;
315 cr0 |= (cfg->dfs - 1);
319 cr0 |= cfg->tmode << SPI_TMOD_OFFSET;
322 cr0 |= cfg->tmode << DWC_SSI_CTRLR0_TMOD_OFFSET;
324 dw_writel(dws, DW_SPI_CTRLR0, cr0);
795 chip->cr0 = dw_spi_prepare_cr0(dws, spi);