Lines Matching refs:dln2
11 #include <linux/mfd/dln2.h>
101 static int dln2_spi_enable(struct dln2_spi *dln2, bool enable)
110 tx.port = dln2->port;
120 return dln2_transfer_tx(dln2->pdev, cmd, &tx, len);
131 static int dln2_spi_cs_set(struct dln2_spi *dln2, u8 cs_mask)
138 tx.port = dln2->port;
147 return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_SS, &tx, sizeof(tx));
153 static int dln2_spi_cs_set_one(struct dln2_spi *dln2, u8 cs)
155 return dln2_spi_cs_set(dln2, BIT(cs));
161 static int dln2_spi_cs_enable(struct dln2_spi *dln2, u8 cs_mask, bool enable)
169 tx.port = dln2->port;
173 return dln2_transfer_tx(dln2->pdev, cmd, &tx, sizeof(tx));
176 static int dln2_spi_cs_enable_all(struct dln2_spi *dln2, bool enable)
178 u8 cs_mask = GENMASK(dln2->master->num_chipselect - 1, 0);
180 return dln2_spi_cs_enable(dln2, cs_mask, enable);
183 static int dln2_spi_get_cs_num(struct dln2_spi *dln2, u16 *cs_num)
194 tx.port = dln2->port;
195 ret = dln2_transfer(dln2->pdev, DLN2_SPI_GET_SS_COUNT, &tx, sizeof(tx),
204 dev_dbg(&dln2->pdev->dev, "cs_num = %d\n", *cs_num);
209 static int dln2_spi_get_speed(struct dln2_spi *dln2, u16 cmd, u32 *freq)
220 tx.port = dln2->port;
222 ret = dln2_transfer(dln2->pdev, cmd, &tx, sizeof(tx), &rx, &rx_len);
236 static int dln2_spi_get_speed_range(struct dln2_spi *dln2, u32 *fmin, u32 *fmax)
240 ret = dln2_spi_get_speed(dln2, DLN2_SPI_GET_MIN_FREQUENCY, fmin);
244 ret = dln2_spi_get_speed(dln2, DLN2_SPI_GET_MAX_FREQUENCY, fmax);
248 dev_dbg(&dln2->pdev->dev, "freq_min = %d, freq_max = %d\n",
258 static int dln2_spi_set_speed(struct dln2_spi *dln2, u32 speed)
270 tx.port = dln2->port;
273 ret = dln2_transfer(dln2->pdev, DLN2_SPI_SET_FREQUENCY, &tx, sizeof(tx),
286 static int dln2_spi_set_mode(struct dln2_spi *dln2, u8 mode)
293 tx.port = dln2->port;
296 return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_MODE, &tx, sizeof(tx));
302 static int dln2_spi_set_bpw(struct dln2_spi *dln2, u8 bpw)
309 tx.port = dln2->port;
312 return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_FRAME_SIZE,
316 static int dln2_spi_get_supported_frame_sizes(struct dln2_spi *dln2,
326 } *rx = dln2->buf;
330 tx.port = dln2->port;
332 ret = dln2_transfer(dln2->pdev, DLN2_SPI_GET_SUPPORTED_FRAME_SIZES,
345 dev_dbg(&dln2->pdev->dev, "bpw_mask = 0x%X\n", *bpw_mask);
418 static int dln2_spi_write_one(struct dln2_spi *dln2, const u8 *data,
426 } __packed *tx = dln2->buf;
434 tx->port = dln2->port;
438 dln2_spi_copy_to_buf(tx->buf, data, data_len, dln2->bpw);
441 return dln2_transfer_tx(dln2->pdev, DLN2_SPI_WRITE, tx, tx_len);
447 static int dln2_spi_read_one(struct dln2_spi *dln2, u8 *data,
459 } __packed *rx = dln2->buf;
467 tx.port = dln2->port;
471 ret = dln2_transfer(dln2->pdev, DLN2_SPI_READ, &tx, sizeof(tx),
480 dln2_spi_copy_from_buf(data, rx->buf, data_len, dln2->bpw);
488 static int dln2_spi_read_write_one(struct dln2_spi *dln2, const u8 *tx_data,
515 tx = dln2->buf;
516 rx = dln2->buf;
518 tx->port = dln2->port;
522 dln2_spi_copy_to_buf(tx->buf, tx_data, data_len, dln2->bpw);
527 ret = dln2_transfer(dln2->pdev, DLN2_SPI_READ_WRITE, tx, tx_len,
536 dln2_spi_copy_from_buf(rx_data, rx->buf, data_len, dln2->bpw);
545 static int dln2_spi_rdwr(struct dln2_spi *dln2, const u8 *tx_data,
565 ret = dln2_spi_read_write_one(dln2,
570 ret = dln2_spi_write_one(dln2,
574 ret = dln2_spi_read_one(dln2,
594 struct dln2_spi *dln2 = spi_master_get_devdata(master);
597 if (dln2->cs != spi->chip_select) {
598 ret = dln2_spi_cs_set_one(dln2, spi->chip_select);
602 dln2->cs = spi->chip_select;
608 static int dln2_spi_transfer_setup(struct dln2_spi *dln2, u32 speed,
614 bus_setup_change = dln2->speed != speed || dln2->mode != mode ||
615 dln2->bpw != bpw;
620 ret = dln2_spi_enable(dln2, false);
624 if (dln2->speed != speed) {
625 ret = dln2_spi_set_speed(dln2, speed);
629 dln2->speed = speed;
632 if (dln2->mode != mode) {
633 ret = dln2_spi_set_mode(dln2, mode & 0x3);
637 dln2->mode = mode;
640 if (dln2->bpw != bpw) {
641 ret = dln2_spi_set_bpw(dln2, bpw);
645 dln2->bpw = bpw;
648 return dln2_spi_enable(dln2, true);
655 struct dln2_spi *dln2 = spi_master_get_devdata(master);
659 status = dln2_spi_transfer_setup(dln2, xfer->speed_hz,
663 dev_err(&dln2->pdev->dev, "Cannot setup transfer\n");
670 status = dln2_spi_rdwr(dln2, xfer->tx_buf, xfer->rx_buf,
673 dev_err(&dln2->pdev->dev, "write/read failed!\n");
681 struct dln2_spi *dln2;
686 master = spi_alloc_master(&pdev->dev, sizeof(*dln2));
692 dln2 = spi_master_get_devdata(master);
694 dln2->buf = devm_kmalloc(&pdev->dev, DLN2_SPI_BUF_SIZE, GFP_KERNEL);
695 if (!dln2->buf) {
700 dln2->master = master;
701 dln2->master->dev.of_node = dev->of_node;
702 dln2->pdev = pdev;
703 dln2->port = pdata->port;
705 dln2->cs = 0xff;
706 dln2->mode = 0xff;
709 ret = dln2_spi_enable(dln2, false);
715 ret = dln2_spi_get_cs_num(dln2, &master->num_chipselect);
721 ret = dln2_spi_get_speed_range(dln2,
729 ret = dln2_spi_get_supported_frame_sizes(dln2,
736 ret = dln2_spi_cs_enable_all(dln2, true);
749 ret = dln2_spi_enable(dln2, true);
773 if (dln2_spi_enable(dln2, false) < 0)
784 struct dln2_spi *dln2 = spi_master_get_devdata(master);
788 if (dln2_spi_enable(dln2, false) < 0)
799 struct dln2_spi *dln2 = spi_master_get_devdata(master);
806 ret = dln2_spi_enable(dln2, false);
815 dln2->cs = 0xff;
816 dln2->speed = 0;
817 dln2->bpw = 0;
818 dln2->mode = 0xff;
827 struct dln2_spi *dln2 = spi_master_get_devdata(master);
830 ret = dln2_spi_cs_enable_all(dln2, true);
834 ret = dln2_spi_enable(dln2, true);
847 struct dln2_spi *dln2 = spi_master_get_devdata(master);
849 return dln2_spi_enable(dln2, false);
855 struct dln2_spi *dln2 = spi_master_get_devdata(master);
857 return dln2_spi_enable(dln2, true);
869 .name = "dln2-spi",
880 MODULE_ALIAS("platform:dln2-spi");