Lines Matching defs:dspi
135 static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi)
137 if (dspi->rx) {
138 u8 *rx = dspi->rx;
140 dspi->rx = rx;
144 static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi)
146 if (dspi->rx) {
147 u16 *rx = dspi->rx;
149 dspi->rx = rx;
153 static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)
157 if (dspi->tx) {
158 const u8 *tx = dspi->tx;
161 dspi->tx = tx;
166 static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi)
170 if (dspi->tx) {
171 const u16 *tx = dspi->tx;
174 dspi->tx = tx;
200 struct davinci_spi *dspi;
205 dspi = spi_master_get_devdata(spi->master);
228 iowrite16(spidat1, dspi->base + SPIDAT1 + 2);
233 * @dspi: the controller data
242 static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
248 ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz) - 1;
250 if (ret < dspi->prescaler_limit || ret > 255)
269 struct davinci_spi *dspi;
275 dspi = spi_master_get_devdata(spi->master);
294 dspi->get_rx = davinci_spi_rx_buf_u8;
295 dspi->get_tx = davinci_spi_tx_buf_u8;
296 dspi->bytes_per_word[spi->chip_select] = 1;
298 dspi->get_rx = davinci_spi_rx_buf_u16;
299 dspi->get_tx = davinci_spi_tx_buf_u16;
300 dspi->bytes_per_word[spi->chip_select] = 2;
308 prescale = davinci_spi_get_prescale(dspi, hz);
344 if (dspi->version == SPI_VERSION_2) {
371 iowrite32(delay, dspi->base + SPIDELAY);
374 iowrite32(spifmt, dspi->base + SPIFMT0);
383 struct davinci_spi *dspi = spi_master_get_devdata(spi->master);
396 if (dspi->dma_rx && dspi->dma_tx)
411 struct davinci_spi *dspi;
415 dspi = spi_master_get_devdata(spi->master);
422 set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
426 set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
429 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
431 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
461 static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
463 struct device *sdev = dspi->bitbang.master->dev.parent;
478 if (dspi->version == SPI_VERSION_2) {
502 * @dspi: the controller data
507 static int davinci_spi_process_events(struct davinci_spi *dspi)
511 buf = ioread32(dspi->base + SPIBUF);
513 if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
514 dspi->get_rx(buf & 0xFFFF, dspi);
515 dspi->rcount--;
518 status = ioread32(dspi->base + SPIFLG);
525 if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
526 spidat1 = ioread32(dspi->base + SPIDAT1);
527 dspi->wcount--;
529 spidat1 |= 0xFFFF & dspi->get_tx(dspi);
530 iowrite32(spidat1, dspi->base + SPIDAT1);
539 struct davinci_spi *dspi = (struct davinci_spi *)data;
541 dspi->rcount = 0;
543 if (!dspi->wcount && !dspi->rcount)
544 complete(&dspi->done);
549 struct davinci_spi *dspi = (struct davinci_spi *)data;
551 dspi->wcount = 0;
553 if (!dspi->wcount && !dspi->rcount)
554 complete(&dspi->done);
568 struct davinci_spi *dspi;
575 dspi = spi_master_get_devdata(spi->master);
576 pdata = &dspi->pdata;
582 data_type = dspi->bytes_per_word[spi->chip_select];
584 dspi->tx = t->tx_buf;
585 dspi->rx = t->rx_buf;
586 dspi->wcount = t->len / data_type;
587 dspi->rcount = dspi->wcount;
589 spidat1 = ioread32(dspi->base + SPIDAT1);
591 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
592 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
594 reinit_completion(&dspi->done);
598 set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
600 dspi->wcount--;
601 tx_data = dspi->get_tx(dspi);
604 iowrite32(spidat1, dspi->base + SPIDAT1);
608 .src_addr = (unsigned long)dspi->pbase + SPIBUF,
614 .dst_addr = (unsigned long)dspi->pbase + SPIDAT1,
621 dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf);
622 dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf);
624 rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx,
640 txdesc = dmaengine_prep_slave_sg(dspi->dma_tx,
647 rxdesc->callback_param = (void *)dspi;
649 txdesc->callback_param = (void *)dspi;
652 iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
657 dma_async_issue_pending(dspi->dma_rx);
658 dma_async_issue_pending(dspi->dma_tx);
660 set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
665 if (wait_for_completion_timeout(&dspi->done, HZ) == 0)
668 while (dspi->rcount > 0 || dspi->wcount > 0) {
669 errors = davinci_spi_process_events(dspi);
676 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
678 clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
680 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
681 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
688 ret = davinci_spi_check_error(dspi, errors);
694 if (dspi->rcount != 0 || dspi->wcount != 0) {
731 struct davinci_spi *dspi = data;
734 status = davinci_spi_process_events(dspi);
736 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
738 if ((!dspi->rcount && !dspi->wcount) || status)
739 complete(&dspi->done);
744 static int davinci_spi_request_dma(struct davinci_spi *dspi)
746 struct device *sdev = dspi->bitbang.master->dev.parent;
748 dspi->dma_rx = dma_request_chan(sdev, "rx");
749 if (IS_ERR(dspi->dma_rx))
750 return PTR_ERR(dspi->dma_rx);
752 dspi->dma_tx = dma_request_chan(sdev, "tx");
753 if (IS_ERR(dspi->dma_tx)) {
754 dma_release_channel(dspi->dma_rx);
755 return PTR_ERR(dspi->dma_tx);
804 * @dspi: ptr to driver data
806 * Parses and populates pdata in dspi from device tree bindings.
811 struct davinci_spi *dspi)
819 pdata = &dspi->pdata;
845 struct davinci_spi *dspi)
865 struct davinci_spi *dspi;
879 dspi = spi_master_get_devdata(master);
883 dspi->pdata = *pdata;
885 /* update dspi pdata with that from the DT */
886 ret = spi_davinci_get_pdata(pdev, dspi);
891 /* pdata in dspi is now updated and point pdata to that */
892 pdata = &dspi->pdata;
894 dspi->bytes_per_word = devm_kcalloc(&pdev->dev,
896 sizeof(*dspi->bytes_per_word),
898 if (dspi->bytes_per_word == NULL) {
909 dspi->pbase = r->start;
911 dspi->base = devm_ioremap_resource(&pdev->dev, r);
912 if (IS_ERR(dspi->base)) {
913 ret = PTR_ERR(dspi->base);
917 init_completion(&dspi->done);
924 dspi->irq = ret;
926 ret = devm_request_threaded_irq(&pdev->dev, dspi->irq, davinci_spi_irq,
927 dummy_thread_fn, 0, dev_name(&pdev->dev), dspi);
931 dspi->bitbang.master = master;
933 dspi->clk = devm_clk_get(&pdev->dev, NULL);
934 if (IS_ERR(dspi->clk)) {
938 ret = clk_prepare_enable(dspi->clk);
952 dspi->bitbang.chipselect = davinci_spi_chipselect;
953 dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;
954 dspi->prescaler_limit = pdata->prescaler_limit;
955 dspi->version = pdata->version;
957 dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_WORD;
958 if (dspi->version == SPI_VERSION_2)
959 dspi->bitbang.flags |= SPI_READY;
961 dspi->bitbang.txrx_bufs = davinci_spi_bufs;
963 ret = davinci_spi_request_dma(dspi);
968 dspi->dma_rx = NULL;
969 dspi->dma_tx = NULL;
972 dspi->get_rx = davinci_spi_rx_buf_u8;
973 dspi->get_tx = davinci_spi_tx_buf_u8;
976 iowrite32(0, dspi->base + SPIGCR0);
978 iowrite32(1, dspi->base + SPIGCR0);
982 iowrite32(spipc0, dspi->base + SPIPC0);
985 iowrite32(SPI_INTLVL_1, dspi->base + SPILVL);
987 iowrite32(SPI_INTLVL_0, dspi->base + SPILVL);
989 iowrite32(CS_DEFAULT, dspi->base + SPIDEF);
992 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);
993 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
994 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
996 ret = spi_bitbang_start(&dspi->bitbang);
1000 dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base);
1005 if (dspi->dma_rx) {
1006 dma_release_channel(dspi->dma_rx);
1007 dma_release_channel(dspi->dma_tx);
1010 clk_disable_unprepare(dspi->clk);
1028 struct davinci_spi *dspi;
1032 dspi = spi_master_get_devdata(master);
1034 spi_bitbang_stop(&dspi->bitbang);
1036 clk_disable_unprepare(dspi->clk);
1038 if (dspi->dma_rx) {
1039 dma_release_channel(dspi->dma_rx);
1040 dma_release_channel(dspi->dma_tx);