Lines Matching refs:mcfqspi
23 #include <asm/mcfqspi.h>
25 #define DRIVER_NAME "mcfqspi"
59 struct mcfqspi {
68 static void mcfqspi_wr_qmr(struct mcfqspi *mcfqspi, u16 val)
70 writew(val, mcfqspi->iobase + MCFQSPI_QMR);
73 static void mcfqspi_wr_qdlyr(struct mcfqspi *mcfqspi, u16 val)
75 writew(val, mcfqspi->iobase + MCFQSPI_QDLYR);
78 static u16 mcfqspi_rd_qdlyr(struct mcfqspi *mcfqspi)
80 return readw(mcfqspi->iobase + MCFQSPI_QDLYR);
83 static void mcfqspi_wr_qwr(struct mcfqspi *mcfqspi, u16 val)
85 writew(val, mcfqspi->iobase + MCFQSPI_QWR);
88 static void mcfqspi_wr_qir(struct mcfqspi *mcfqspi, u16 val)
90 writew(val, mcfqspi->iobase + MCFQSPI_QIR);
93 static void mcfqspi_wr_qar(struct mcfqspi *mcfqspi, u16 val)
95 writew(val, mcfqspi->iobase + MCFQSPI_QAR);
98 static void mcfqspi_wr_qdr(struct mcfqspi *mcfqspi, u16 val)
100 writew(val, mcfqspi->iobase + MCFQSPI_QDR);
103 static u16 mcfqspi_rd_qdr(struct mcfqspi *mcfqspi)
105 return readw(mcfqspi->iobase + MCFQSPI_QDR);
108 static void mcfqspi_cs_select(struct mcfqspi *mcfqspi, u8 chip_select,
111 mcfqspi->cs_control->select(mcfqspi->cs_control, chip_select, cs_high);
114 static void mcfqspi_cs_deselect(struct mcfqspi *mcfqspi, u8 chip_select,
117 mcfqspi->cs_control->deselect(mcfqspi->cs_control, chip_select, cs_high);
120 static int mcfqspi_cs_setup(struct mcfqspi *mcfqspi)
122 return (mcfqspi->cs_control->setup) ?
123 mcfqspi->cs_control->setup(mcfqspi->cs_control) : 0;
126 static void mcfqspi_cs_teardown(struct mcfqspi *mcfqspi)
128 if (mcfqspi->cs_control->teardown)
129 mcfqspi->cs_control->teardown(mcfqspi->cs_control);
137 static bool mcfqspi_qdlyr_spe(struct mcfqspi *mcfqspi)
139 return mcfqspi_rd_qdlyr(mcfqspi) & MCFQSPI_QDLYR_SPE;
144 struct mcfqspi *mcfqspi = dev_id;
147 mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE | MCFQSPI_QIR_SPIF);
148 wake_up(&mcfqspi->waitq);
153 static void mcfqspi_transfer_msg8(struct mcfqspi *mcfqspi, unsigned count,
160 mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF);
162 mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE);
164 mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF);
167 mcfqspi_wr_qdr(mcfqspi, *txbuf++);
170 mcfqspi_wr_qdr(mcfqspi, 0);
175 mcfqspi_wr_qwr(mcfqspi, 0x700);
176 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
179 wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
180 mcfqspi_wr_qwr(mcfqspi, qwr);
181 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
183 mcfqspi_wr_qar(mcfqspi,
186 *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
190 mcfqspi_wr_qar(mcfqspi,
193 mcfqspi_wr_qdr(mcfqspi, *txbuf++);
199 wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
200 mcfqspi_wr_qwr(mcfqspi, qwr);
201 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
203 mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
205 *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
209 mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8);
210 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
212 wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
214 mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
216 *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
220 static void mcfqspi_transfer_msg16(struct mcfqspi *mcfqspi, unsigned count,
227 mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF);
229 mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE);
231 mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF);
234 mcfqspi_wr_qdr(mcfqspi, *txbuf++);
237 mcfqspi_wr_qdr(mcfqspi, 0);
242 mcfqspi_wr_qwr(mcfqspi, 0x700);
243 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
246 wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
247 mcfqspi_wr_qwr(mcfqspi, qwr);
248 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
250 mcfqspi_wr_qar(mcfqspi,
253 *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
257 mcfqspi_wr_qar(mcfqspi,
260 mcfqspi_wr_qdr(mcfqspi, *txbuf++);
266 wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
267 mcfqspi_wr_qwr(mcfqspi, qwr);
268 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
270 mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
272 *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
276 mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8);
277 mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
279 wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
281 mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
283 *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
289 struct mcfqspi *mcfqspi = spi_master_get_devdata(spi->master);
293 mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high);
295 mcfqspi_cs_deselect(mcfqspi, spi->chip_select, cs_high);
302 struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
311 mcfqspi_wr_qmr(mcfqspi, qmr);
313 mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE);
315 mcfqspi_transfer_msg8(mcfqspi, t->len, t->tx_buf, t->rx_buf);
317 mcfqspi_transfer_msg16(mcfqspi, t->len / 2, t->tx_buf,
319 mcfqspi_wr_qir(mcfqspi, 0);
341 struct mcfqspi *mcfqspi;
356 master = spi_alloc_master(&pdev->dev, sizeof(*mcfqspi));
362 mcfqspi = spi_master_get_devdata(master);
364 mcfqspi->iobase = devm_platform_ioremap_resource(pdev, 0);
365 if (IS_ERR(mcfqspi->iobase)) {
366 status = PTR_ERR(mcfqspi->iobase);
370 mcfqspi->irq = platform_get_irq(pdev, 0);
371 if (mcfqspi->irq < 0) {
377 status = devm_request_irq(&pdev->dev, mcfqspi->irq, mcfqspi_irq_handler,
378 0, pdev->name, mcfqspi);
384 mcfqspi->clk = devm_clk_get(&pdev->dev, "qspi_clk");
385 if (IS_ERR(mcfqspi->clk)) {
387 status = PTR_ERR(mcfqspi->clk);
390 clk_prepare_enable(mcfqspi->clk);
395 mcfqspi->cs_control = pdata->cs_control;
396 status = mcfqspi_cs_setup(mcfqspi);
402 init_waitqueue_head(&mcfqspi->waitq);
426 mcfqspi_cs_teardown(mcfqspi);
428 clk_disable_unprepare(mcfqspi->clk);
440 struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
444 mcfqspi_wr_qmr(mcfqspi, MCFQSPI_QMR_MSTR);
446 mcfqspi_cs_teardown(mcfqspi);
447 clk_disable_unprepare(mcfqspi->clk);
456 struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
463 clk_disable(mcfqspi->clk);
471 struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
473 clk_enable(mcfqspi->clk);
483 struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
485 clk_disable(mcfqspi->clk);
493 struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
495 clk_enable(mcfqspi->clk);