Lines Matching refs:reg
237 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr)
241 return readl_relaxed_poll_timeout(reg, val,
248 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
250 return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB);
255 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
257 reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
258 return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
324 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
330 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
332 reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
333 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
357 unsigned int reg;
368 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
373 reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
376 reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
378 status = cqspi_exec_flash_cmd(cqspi, reg);
382 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
386 memcpy(rxbuf, ®, read_len);
390 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
393 memcpy(rxbuf, ®, read_len);
407 unsigned int reg;
418 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
421 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
422 reg |= ((op->addr.nbytes - 1) &
430 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
431 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
447 return cqspi_exec_flash_cmd(cqspi, reg);
456 unsigned int reg;
458 reg = op->cmd.opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
459 reg |= cqspi_calc_rdreg(f_pdata);
467 reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
470 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
473 reg = readl(reg_base + CQSPI_REG_SIZE);
474 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
475 reg |= (op->addr.nbytes - 1);
476 writel(reg, reg_base + CQSPI_REG_SIZE);
575 unsigned int reg;
580 reg = op->cmd.opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
581 writel(reg, reg_base + CQSPI_REG_WR_INSTR);
582 reg = cqspi_calc_rdreg(f_pdata);
583 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
585 reg = readl(reg_base + CQSPI_REG_SIZE);
586 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
587 reg |= (op->addr.nbytes - 1);
588 writel(reg, reg_base + CQSPI_REG_SIZE);
689 unsigned int reg;
691 reg = readl(reg_base + CQSPI_REG_CONFIG);
693 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
695 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
706 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
708 reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
710 writel(reg, reg_base + CQSPI_REG_CONFIG);
730 unsigned int reg;
745 reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
747 reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
749 reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
751 reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
753 writel(reg, iobase + CQSPI_REG_DELAY);
760 u32 reg, div;
765 reg = readl(reg_base + CQSPI_REG_CONFIG);
766 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
767 reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
768 writel(reg, reg_base + CQSPI_REG_CONFIG);
776 unsigned int reg;
778 reg = readl(reg_base + CQSPI_REG_READCAPTURE);
781 reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
783 reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
785 reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
788 reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
791 writel(reg, reg_base + CQSPI_REG_READCAPTURE);
797 unsigned int reg;
799 reg = readl(reg_base + CQSPI_REG_CONFIG);
802 reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
804 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
806 writel(reg, reg_base + CQSPI_REG_CONFIG);
1080 u32 reg;
1105 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1106 reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
1107 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1154 ret = of_property_read_u32(np, "reg", &cs);