Lines Matching refs:cqspi
45 struct cqspi_st *cqspi;
246 static bool cqspi_is_idle(struct cqspi_st *cqspi)
248 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
253 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
255 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
263 struct cqspi_st *cqspi = dev;
267 irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
270 writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
275 complete(&cqspi->transfer_complete);
291 static int cqspi_wait_idle(struct cqspi_st *cqspi)
304 if (cqspi_is_idle(cqspi))
314 dev_err(&cqspi->pdev->dev,
324 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
326 void __iomem *reg_base = cqspi->iobase;
339 dev_err(&cqspi->pdev->dev,
345 return cqspi_wait_idle(cqspi);
351 struct cqspi_st *cqspi = f_pdata->cqspi;
352 void __iomem *reg_base = cqspi->iobase;
362 dev_err(&cqspi->pdev->dev,
378 status = cqspi_exec_flash_cmd(cqspi, reg);
402 struct cqspi_st *cqspi = f_pdata->cqspi;
403 void __iomem *reg_base = cqspi->iobase;
412 dev_err(&cqspi->pdev->dev,
447 return cqspi_exec_flash_cmd(cqspi, reg);
453 struct cqspi_st *cqspi = f_pdata->cqspi;
454 void __iomem *reg_base = cqspi->iobase;
484 struct cqspi_st *cqspi = f_pdata->cqspi;
485 struct device *dev = &cqspi->pdev->dev;
486 void __iomem *reg_base = cqspi->iobase;
487 void __iomem *ahb_base = cqspi->ahb_base;
502 reinit_completion(&cqspi->transfer_complete);
507 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
511 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
521 bytes_to_read *= cqspi->fifo_width;
539 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
543 reinit_completion(&cqspi->transfer_complete);
576 struct cqspi_st *cqspi = f_pdata->cqspi;
577 void __iomem *reg_base = cqspi->iobase;
596 struct cqspi_st *cqspi = f_pdata->cqspi;
597 struct device *dev = &cqspi->pdev->dev;
598 void __iomem *reg_base = cqspi->iobase;
611 reinit_completion(&cqspi->transfer_complete);
621 if (cqspi->wr_delay)
622 ndelay(cqspi->wr_delay);
632 iowrite32_rep(cqspi->ahb_base, txbuf, write_words);
639 iowrite32(temp, cqspi->ahb_base);
643 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
653 reinit_completion(&cqspi->transfer_complete);
670 cqspi_wait_idle(cqspi);
686 struct cqspi_st *cqspi = f_pdata->cqspi;
687 void __iomem *reg_base = cqspi->iobase;
692 if (cqspi->is_decoded_cs) {
726 struct cqspi_st *cqspi = f_pdata->cqspi;
727 void __iomem *iobase = cqspi->iobase;
728 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
734 tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
756 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
758 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
759 void __iomem *reg_base = cqspi->iobase;
763 div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
771 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
775 void __iomem *reg_base = cqspi->iobase;
794 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
796 void __iomem *reg_base = cqspi->iobase;
812 struct cqspi_st *cqspi = f_pdata->cqspi;
813 int switch_cs = (cqspi->current_cs != f_pdata->cs);
814 int switch_ck = (cqspi->sclk != sclk);
817 cqspi_controller_enable(cqspi, 0);
821 cqspi->current_cs = f_pdata->cs;
827 cqspi->sclk = sclk;
828 cqspi_config_baudrate_div(cqspi);
830 cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
835 cqspi_controller_enable(cqspi, 1);
870 struct cqspi_st *cqspi = f_pdata->cqspi;
884 if (cqspi->use_direct_mode && ((to + len) <= cqspi->ahb_size)) {
885 memcpy_toio(cqspi->ahb_base + to, buf, len);
886 return cqspi_wait_idle(cqspi);
894 struct cqspi_st *cqspi = param;
896 complete(&cqspi->rx_dma_complete);
902 struct cqspi_st *cqspi = f_pdata->cqspi;
903 struct device *dev = &cqspi->pdev->dev;
905 dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from;
912 if (!cqspi->rx_chan || !virt_addr_valid(buf)) {
913 memcpy_fromio(buf, cqspi->ahb_base + from, len);
917 ddev = cqspi->rx_chan->device->dev;
923 tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src,
932 tx->callback_param = cqspi;
934 reinit_completion(&cqspi->rx_dma_complete);
943 dma_async_issue_pending(cqspi->rx_chan);
944 if (!wait_for_completion_timeout(&cqspi->rx_dma_complete,
946 dmaengine_terminate_sync(cqspi->rx_chan);
961 struct cqspi_st *cqspi = f_pdata->cqspi;
975 if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size))
983 struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master);
986 f_pdata = &cqspi->f_pdata[mem->spi->chip_select];
1050 static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
1052 struct device *dev = &cqspi->pdev->dev;
1055 cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1057 if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1062 if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1068 &cqspi->trigger_address)) {
1073 cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
1078 static void cqspi_controller_init(struct cqspi_st *cqspi)
1082 cqspi_controller_enable(cqspi, 0);
1085 writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1088 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1091 writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1094 writel(cqspi->trigger_address,
1095 cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1098 writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1099 cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1101 writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1102 cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1105 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1107 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1109 cqspi_controller_enable(cqspi, 1);
1112 static int cqspi_request_mmap_dma(struct cqspi_st *cqspi)
1119 cqspi->rx_chan = dma_request_chan_by_mask(&mask);
1120 if (IS_ERR(cqspi->rx_chan)) {
1121 int ret = PTR_ERR(cqspi->rx_chan);
1122 cqspi->rx_chan = NULL;
1123 return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n");
1125 init_completion(&cqspi->rx_dma_complete);
1132 struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master);
1133 struct device *dev = &cqspi->pdev->dev;
1143 static int cqspi_setup_flash(struct cqspi_st *cqspi)
1145 struct platform_device *pdev = cqspi->pdev;
1165 f_pdata = &cqspi->f_pdata[cs];
1166 f_pdata->cqspi = cqspi;
1184 struct cqspi_st *cqspi;
1189 master = spi_alloc_master(&pdev->dev, sizeof(*cqspi));
1198 cqspi = spi_master_get_devdata(master);
1200 cqspi->pdev = pdev;
1201 platform_set_drvdata(pdev, cqspi);
1204 ret = cqspi_of_get_pdata(cqspi);
1212 cqspi->clk = devm_clk_get(dev, NULL);
1213 if (IS_ERR(cqspi->clk)) {
1215 ret = PTR_ERR(cqspi->clk);
1221 cqspi->iobase = devm_ioremap_resource(dev, res);
1222 if (IS_ERR(cqspi->iobase)) {
1224 ret = PTR_ERR(cqspi->iobase);
1230 cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb);
1231 if (IS_ERR(cqspi->ahb_base)) {
1233 ret = PTR_ERR(cqspi->ahb_base);
1236 cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
1237 cqspi->ahb_size = resource_size(res_ahb);
1239 init_completion(&cqspi->transfer_complete);
1255 ret = clk_prepare_enable(cqspi->clk);
1282 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1286 cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
1287 cqspi->master_ref_clk_hz);
1291 cqspi->use_direct_mode = true;
1295 pdev->name, cqspi);
1301 cqspi_wait_idle(cqspi);
1302 cqspi_controller_init(cqspi);
1303 cqspi->current_cs = -1;
1304 cqspi->sclk = 0;
1306 ret = cqspi_setup_flash(cqspi);
1312 if (cqspi->use_direct_mode) {
1313 ret = cqspi_request_mmap_dma(cqspi);
1326 cqspi_controller_enable(cqspi, 0);
1328 clk_disable_unprepare(cqspi->clk);
1339 struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1341 cqspi_controller_enable(cqspi, 0);
1343 if (cqspi->rx_chan)
1344 dma_release_channel(cqspi->rx_chan);
1346 clk_disable_unprepare(cqspi->clk);
1357 struct cqspi_st *cqspi = dev_get_drvdata(dev);
1362 cqspi_controller_enable(cqspi, 0);
1364 clk_disable_unprepare(cqspi->clk);
1371 struct cqspi_st *cqspi = dev_get_drvdata(dev);
1374 clk_prepare_enable(cqspi->clk);
1375 cqspi_wait_idle(cqspi);
1376 cqspi_controller_init(cqspi);
1378 cqspi->current_cs = -1;
1379 cqspi->sclk = 0;