Lines Matching defs:reg_base
326 void __iomem *reg_base = cqspi->iobase;
330 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
333 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
336 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
352 void __iomem *reg_base = cqspi->iobase;
371 writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
382 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
390 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
403 void __iomem *reg_base = cqspi->iobase;
426 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);
437 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
443 writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);
454 void __iomem *reg_base = cqspi->iobase;
470 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
473 reg = readl(reg_base + CQSPI_REG_SIZE);
476 writel(reg, reg_base + CQSPI_REG_SIZE);
486 void __iomem *reg_base = cqspi->iobase;
494 writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
495 writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
498 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
500 writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
504 reg_base + CQSPI_REG_INDIRECTRD);
547 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
555 writel(0, reg_base + CQSPI_REG_IRQMASK);
558 writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
564 writel(0, reg_base + CQSPI_REG_IRQMASK);
568 reg_base + CQSPI_REG_INDIRECTRD);
577 void __iomem *reg_base = cqspi->iobase;
581 writel(reg, reg_base + CQSPI_REG_WR_INSTR);
583 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
585 reg = readl(reg_base + CQSPI_REG_SIZE);
588 writel(reg, reg_base + CQSPI_REG_SIZE);
598 void __iomem *reg_base = cqspi->iobase;
603 writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
604 writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
607 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
609 writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
613 reg_base + CQSPI_REG_INDIRECTWR);
657 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
665 writel(0, reg_base + CQSPI_REG_IRQMASK);
668 writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
676 writel(0, reg_base + CQSPI_REG_IRQMASK);
680 reg_base + CQSPI_REG_INDIRECTWR);
687 void __iomem *reg_base = cqspi->iobase;
691 reg = readl(reg_base + CQSPI_REG_CONFIG);
710 writel(reg, reg_base + CQSPI_REG_CONFIG);
759 void __iomem *reg_base = cqspi->iobase;
765 reg = readl(reg_base + CQSPI_REG_CONFIG);
768 writel(reg, reg_base + CQSPI_REG_CONFIG);
775 void __iomem *reg_base = cqspi->iobase;
778 reg = readl(reg_base + CQSPI_REG_READCAPTURE);
791 writel(reg, reg_base + CQSPI_REG_READCAPTURE);
796 void __iomem *reg_base = cqspi->iobase;
799 reg = readl(reg_base + CQSPI_REG_CONFIG);
806 writel(reg, reg_base + CQSPI_REG_CONFIG);