Lines Matching refs:bs
114 static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned int cs,
119 mutex_lock(&bs->bus_mutex);
120 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
123 if (active == !(bs->cs_polarity & BIT(cs)))
126 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
127 mutex_unlock(&bs->bus_mutex);
130 static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs,
136 reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
138 bs->regs + HSSPI_PROFILE_CLK_CTRL_REG(profile));
140 reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
145 __raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
147 mutex_lock(&bs->bus_mutex);
149 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
153 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
154 mutex_unlock(&bs->bus_mutex);
159 struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
168 bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz);
169 bcm63xx_hsspi_set_cs(bs, spi->chip_select, true);
192 bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
197 reinit_completion(&bs->done);
199 memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step);
203 __raw_writew(opcode | curr_step, bs->fifo);
207 bs->regs + HSSPI_INT_MASK_REG);
213 bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));
215 if (wait_for_completion_timeout(&bs->done, HZ) == 0) {
216 dev_err(&bs->pdev->dev, "transfer timed out!\n");
221 memcpy_fromio(rx, bs->fifo, curr_step);
233 struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
236 reg = __raw_readl(bs->regs +
243 __raw_writel(reg, bs->regs +
246 mutex_lock(&bs->bus_mutex);
247 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
250 if ((reg & GLOBAL_CTRL_CS_POLARITY_MASK) == bs->cs_polarity) {
255 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
259 bs->cs_polarity |= BIT(spi->chip_select);
261 bs->cs_polarity &= ~BIT(spi->chip_select);
263 mutex_unlock(&bs->bus_mutex);
271 struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
293 bcm63xx_hsspi_set_cs(bs, dummy_cs, true);
305 bcm63xx_hsspi_set_cs(bs, spi->chip_select, false);
308 mutex_lock(&bs->bus_mutex);
309 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
311 reg |= bs->cs_polarity;
312 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
313 mutex_unlock(&bs->bus_mutex);
323 struct bcm63xx_hsspi *bs = (struct bcm63xx_hsspi *)dev_id;
325 if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0)
328 __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
329 __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
331 complete(&bs->done);
339 struct bcm63xx_hsspi *bs;
394 master = spi_alloc_master(&pdev->dev, sizeof(*bs));
400 bs = spi_master_get_devdata(master);
401 bs->pdev = pdev;
402 bs->clk = clk;
403 bs->pll_clk = pll_clk;
404 bs->regs = regs;
405 bs->speed_hz = rate;
406 bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0));
408 mutex_init(&bs->bus_mutex);
409 init_completion(&bs->done);
432 __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
435 __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
438 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
439 bs->cs_polarity = reg & GLOBAL_CTRL_CS_POLARITY_MASK;
441 bs->regs + HSSPI_GLOBAL_CTRL_REG);
444 pdev->name, bs);
473 struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
476 __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
477 clk_disable_unprepare(bs->pll_clk);
478 clk_disable_unprepare(bs->clk);
487 struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
490 clk_disable_unprepare(bs->pll_clk);
491 clk_disable_unprepare(bs->clk);
499 struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
502 ret = clk_prepare_enable(bs->clk);
506 if (bs->pll_clk) {
507 ret = clk_prepare_enable(bs->pll_clk);
509 clk_disable_unprepare(bs->clk);