Lines Matching refs:bs
158 static void bcm2835_debugfs_create(struct bcm2835_spi *bs,
169 bs->debugfs_dir = dir;
173 &bs->count_transfer_polling);
175 &bs->count_transfer_irq);
177 &bs->count_transfer_irq_after_polling);
179 &bs->count_transfer_dma);
182 static void bcm2835_debugfs_remove(struct bcm2835_spi *bs)
184 debugfs_remove_recursive(bs->debugfs_dir);
185 bs->debugfs_dir = NULL;
188 static void bcm2835_debugfs_create(struct bcm2835_spi *bs,
193 static void bcm2835_debugfs_remove(struct bcm2835_spi *bs)
198 static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned int reg)
200 return readl(bs->regs + reg);
203 static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned int reg, u32 val)
205 writel(val, bs->regs + reg);
208 static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs)
212 while ((bs->rx_len) &&
213 (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD)) {
214 byte = bcm2835_rd(bs, BCM2835_SPI_FIFO);
215 if (bs->rx_buf)
216 *bs->rx_buf++ = byte;
217 bs->rx_len--;
221 static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs)
225 while ((bs->tx_len) &&
226 (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) {
227 byte = bs->tx_buf ? *bs->tx_buf++ : 0;
228 bcm2835_wr(bs, BCM2835_SPI_FIFO, byte);
229 bs->tx_len--;
235 * @bs: BCM2835 SPI controller
238 * The caller must ensure that @bs->rx_len is greater than or equal to @count,
241 * 32-bit instead of just 8-bit). Moreover @bs->rx_buf must not be %NULL.
243 static inline void bcm2835_rd_fifo_count(struct bcm2835_spi *bs, int count)
248 bs->rx_len -= count;
251 val = bcm2835_rd(bs, BCM2835_SPI_FIFO);
253 memcpy(bs->rx_buf, &val, len);
254 bs->rx_buf += len;
261 * @bs: BCM2835 SPI controller
264 * The caller must ensure that @bs->tx_len is greater than or equal to @count,
269 static inline void bcm2835_wr_fifo_count(struct bcm2835_spi *bs, int count)
274 bs->tx_len -= count;
277 if (bs->tx_buf) {
279 memcpy(&val, bs->tx_buf, len);
280 bs->tx_buf += len;
284 bcm2835_wr(bs, BCM2835_SPI_FIFO, val);
291 * @bs: BCM2835 SPI controller
297 static inline void bcm2835_wait_tx_fifo_empty(struct bcm2835_spi *bs)
299 while (!(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE))
305 * @bs: BCM2835 SPI controller
308 static inline void bcm2835_rd_fifo_blind(struct bcm2835_spi *bs, int count)
312 count = min(count, bs->rx_len);
313 bs->rx_len -= count;
316 val = bcm2835_rd(bs, BCM2835_SPI_FIFO);
317 if (bs->rx_buf)
318 *bs->rx_buf++ = val;
324 * @bs: BCM2835 SPI controller
327 static inline void bcm2835_wr_fifo_blind(struct bcm2835_spi *bs, int count)
331 count = min(count, bs->tx_len);
332 bs->tx_len -= count;
335 val = bs->tx_buf ? *bs->tx_buf++ : 0;
336 bcm2835_wr(bs, BCM2835_SPI_FIFO, val);
340 static void bcm2835_spi_reset_hw(struct bcm2835_spi *bs)
342 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
360 bcm2835_wr(bs, BCM2835_SPI_CS, cs);
362 bcm2835_wr(bs, BCM2835_SPI_DLEN, 0);
367 struct bcm2835_spi *bs = dev_id;
368 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
375 bcm2835_rd_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
377 bcm2835_rd_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE_3_4);
379 if (bs->tx_len && cs & BCM2835_SPI_CS_DONE)
380 bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
383 bcm2835_rd_fifo(bs);
385 bcm2835_wr_fifo(bs);
387 if (!bs->rx_len) {
389 bcm2835_spi_reset_hw(bs);
391 complete(&bs->ctlr->xfer_completion);
402 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
405 bs->count_transfer_irq++;
411 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA);
415 bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
416 bcm2835_wr_fifo(bs);
420 bcm2835_wr(bs, BCM2835_SPI_CS, cs);
430 * @bs: BCM2835 SPI controller
474 struct bcm2835_spi *bs,
479 bs->tfr = tfr;
480 bs->tx_prologue = 0;
481 bs->rx_prologue = 0;
482 bs->tx_spillover = false;
484 if (bs->tx_buf && !sg_is_last(&tfr->tx_sg.sgl[0]))
485 bs->tx_prologue = sg_dma_len(&tfr->tx_sg.sgl[0]) & 3;
487 if (bs->rx_buf && !sg_is_last(&tfr->rx_sg.sgl[0])) {
488 bs->rx_prologue = sg_dma_len(&tfr->rx_sg.sgl[0]) & 3;
490 if (bs->rx_prologue > bs->tx_prologue) {
491 if (!bs->tx_buf || sg_is_last(&tfr->tx_sg.sgl[0])) {
492 bs->tx_prologue = bs->rx_prologue;
494 bs->tx_prologue += 4;
495 bs->tx_spillover =
502 if (!bs->tx_prologue)
506 if (bs->rx_prologue) {
507 bcm2835_wr(bs, BCM2835_SPI_DLEN, bs->rx_prologue);
508 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA
510 bcm2835_wr_fifo_count(bs, bs->rx_prologue);
511 bcm2835_wait_tx_fifo_empty(bs);
512 bcm2835_rd_fifo_count(bs, bs->rx_prologue);
513 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_CLEAR_RX
519 bs->rx_prologue, DMA_FROM_DEVICE);
521 sg_dma_address(&tfr->rx_sg.sgl[0]) += bs->rx_prologue;
522 sg_dma_len(&tfr->rx_sg.sgl[0]) -= bs->rx_prologue;
525 if (!bs->tx_buf)
532 tx_remaining = bs->tx_prologue - bs->rx_prologue;
534 bcm2835_wr(bs, BCM2835_SPI_DLEN, tx_remaining);
535 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA
537 bcm2835_wr_fifo_count(bs, tx_remaining);
538 bcm2835_wait_tx_fifo_empty(bs);
539 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_CLEAR_TX
543 if (likely(!bs->tx_spillover)) {
544 sg_dma_address(&tfr->tx_sg.sgl[0]) += bs->tx_prologue;
545 sg_dma_len(&tfr->tx_sg.sgl[0]) -= bs->tx_prologue;
555 * @bs: BCM2835 SPI controller
561 static void bcm2835_spi_undo_prologue(struct bcm2835_spi *bs)
563 struct spi_transfer *tfr = bs->tfr;
565 if (!bs->tx_prologue)
568 if (bs->rx_prologue) {
569 sg_dma_address(&tfr->rx_sg.sgl[0]) -= bs->rx_prologue;
570 sg_dma_len(&tfr->rx_sg.sgl[0]) += bs->rx_prologue;
573 if (!bs->tx_buf)
576 if (likely(!bs->tx_spillover)) {
577 sg_dma_address(&tfr->tx_sg.sgl[0]) -= bs->tx_prologue;
578 sg_dma_len(&tfr->tx_sg.sgl[0]) += bs->tx_prologue;
580 sg_dma_len(&tfr->tx_sg.sgl[0]) = bs->tx_prologue - 4;
585 bs->tx_prologue = 0;
597 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
605 bs->tx_dma_active = false;
606 bs->rx_dma_active = false;
607 bcm2835_spi_undo_prologue(bs);
610 bcm2835_spi_reset_hw(bs);
625 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
628 while (!(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE))
629 bcm2835_wr(bs, BCM2835_SPI_CS,
630 bs->clear_rx_cs[bs->chip_select]);
632 bs->tx_dma_active = false;
640 if (cmpxchg(&bs->rx_dma_active, true, false))
643 bcm2835_spi_undo_prologue(bs);
644 bcm2835_spi_reset_hw(bs);
653 * @bs: BCM2835 SPI controller
662 struct bcm2835_spi *bs,
702 bs->chip_select = spi->chip_select;
763 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
768 bs->count_transfer_dma++;
774 bcm2835_spi_transfer_prologue(ctlr, tfr, bs, cs);
777 if (bs->tx_buf) {
778 ret = bcm2835_spi_prepare_sg(ctlr, spi, tfr, bs, true);
780 cookie = dmaengine_submit(bs->fill_tx_desc);
787 bcm2835_wr(bs, BCM2835_SPI_DLEN, bs->tx_len);
790 bcm2835_wr(bs, BCM2835_SPI_CS,
793 bs->tx_dma_active = true;
803 if (bs->rx_buf) {
804 ret = bcm2835_spi_prepare_sg(ctlr, spi, tfr, bs, false);
806 cookie = dmaengine_submit(bs->clear_rx_desc[spi->chip_select]);
812 bs->tx_dma_active = false;
818 bs->rx_dma_active = true;
825 if (!bs->rx_buf && !bs->tx_dma_active &&
826 cmpxchg(&bs->rx_dma_active, true, false)) {
828 bcm2835_spi_reset_hw(bs);
835 bcm2835_spi_reset_hw(bs);
836 bcm2835_spi_undo_prologue(bs);
853 struct bcm2835_spi *bs)
860 if (bs->fill_tx_desc)
861 dmaengine_desc_free(bs->fill_tx_desc);
863 if (bs->fill_tx_addr)
865 bs->fill_tx_addr, sizeof(u32),
877 if (bs->clear_rx_desc[i])
878 dmaengine_desc_free(bs->clear_rx_desc[i]);
880 if (bs->clear_rx_addr)
882 bs->clear_rx_addr,
883 sizeof(bs->clear_rx_cs),
892 struct bcm2835_spi *bs)
936 bs->fill_tx_addr = dma_map_page_attrs(ctlr->dma_tx->device->dev,
940 if (dma_mapping_error(ctlr->dma_tx->device->dev, bs->fill_tx_addr)) {
942 bs->fill_tx_addr = 0;
947 bs->fill_tx_desc = dmaengine_prep_dma_cyclic(ctlr->dma_tx,
948 bs->fill_tx_addr,
951 if (!bs->fill_tx_desc) {
957 ret = dmaengine_desc_set_reuse(bs->fill_tx_desc);
977 bs->clear_rx_addr = dma_map_single(ctlr->dma_rx->device->dev,
978 bs->clear_rx_cs,
979 sizeof(bs->clear_rx_cs),
981 if (dma_mapping_error(ctlr->dma_rx->device->dev, bs->clear_rx_addr)) {
983 bs->clear_rx_addr = 0;
989 bs->clear_rx_desc[i] = dmaengine_prep_dma_cyclic(ctlr->dma_rx,
990 bs->clear_rx_addr + i * sizeof(u32),
993 if (!bs->clear_rx_desc[i]) {
999 ret = dmaengine_desc_set_reuse(bs->clear_rx_desc[i]);
1015 bcm2835_dma_release(ctlr, bs);
1032 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
1036 bs->count_transfer_polling++;
1039 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA);
1045 bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
1051 while (bs->rx_len) {
1053 bcm2835_wr_fifo(bs);
1056 bcm2835_rd_fifo(bs);
1061 if (bs->rx_len && time_after(jiffies, timeout)) {
1065 bs->tx_len, bs->rx_len);
1069 bs->count_transfer_irq_after_polling++;
1077 bcm2835_spi_reset_hw(bs);
1086 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
1089 u32 cs = bs->prepare_cs[spi->chip_select];
1094 if (spi_hz >= bs->clk_hz / 2) {
1098 cdiv = DIV_ROUND_UP(bs->clk_hz, spi_hz);
1106 tfr->effective_speed_hz = cdiv ? (bs->clk_hz / cdiv) : (bs->clk_hz / 65536);
1107 bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
1114 bs->tx_buf = tfr->tx_buf;
1115 bs->rx_buf = tfr->rx_buf;
1116 bs->tx_len = tfr->len;
1117 bs->rx_len = tfr->len;
1147 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
1166 bcm2835_wr(bs, BCM2835_SPI_CS, bs->prepare_cs[spi->chip_select]);
1174 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
1179 bs->tx_dma_active = false;
1183 bs->rx_dma_active = false;
1185 bcm2835_spi_undo_prologue(bs);
1188 bcm2835_spi_reset_hw(bs);
1199 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
1220 bs->prepare_cs[spi->chip_select] = cs;
1227 bs->clear_rx_cs[spi->chip_select] = cs |
1232 bs->clear_rx_addr,
1233 sizeof(bs->clear_rx_cs),
1289 struct bcm2835_spi *bs;
1292 ctlr = devm_spi_alloc_master(&pdev->dev, ALIGN(sizeof(*bs),
1309 bs = spi_controller_get_devdata(ctlr);
1310 bs->ctlr = ctlr;
1312 bs->regs = devm_platform_ioremap_resource(pdev, 0);
1313 if (IS_ERR(bs->regs))
1314 return PTR_ERR(bs->regs);
1316 bs->clk = devm_clk_get(&pdev->dev, NULL);
1317 if (IS_ERR(bs->clk))
1318 return dev_err_probe(&pdev->dev, PTR_ERR(bs->clk),
1321 bs->irq = platform_get_irq(pdev, 0);
1322 if (bs->irq <= 0)
1323 return bs->irq ? bs->irq : -ENODEV;
1325 clk_prepare_enable(bs->clk);
1326 bs->clk_hz = clk_get_rate(bs->clk);
1328 err = bcm2835_dma_init(ctlr, &pdev->dev, bs);
1333 bcm2835_wr(bs, BCM2835_SPI_CS,
1336 err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0,
1337 dev_name(&pdev->dev), bs);
1350 bcm2835_debugfs_create(bs, dev_name(&pdev->dev));
1355 bcm2835_dma_release(ctlr, bs);
1357 clk_disable_unprepare(bs->clk);
1364 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
1366 bcm2835_debugfs_remove(bs);
1370 bcm2835_dma_release(ctlr, bs);
1373 bcm2835_wr(bs, BCM2835_SPI_CS,
1376 clk_disable_unprepare(bs->clk);