Lines Matching defs:byte
91 * @tx_buf: pointer whence next transmitted byte is read
92 * @rx_buf: pointer where next received byte is written
210 u8 byte;
214 byte = bcm2835_rd(bs, BCM2835_SPI_FIFO);
216 *bs->rx_buf++ = byte;
223 u8 byte;
227 byte = bs->tx_buf ? *bs->tx_buf++ : 0;
228 bcm2835_wr(bs, BCM2835_SPI_FIFO, byte);
433 * A limitation in DMA mode is that the FIFO must be accessed in 4 byte chunks.
448 * stream of 4 byte chunks, it treats every entry separately: A TX entry is
455 * The residue of 1 byte in the RX FIFO is picked up by DMA. Together with
1120 * there is 1 idle clocks cycles after each byte getting transferred
1121 * so we have 9 cycles/byte. This is used to find the number of Hz
1122 * per byte per polling limit. E.g., we can transfer 1 byte in 30 us