Lines Matching defs:qspi
25 #include "spi-bcm-qspi.h"
234 static inline bool has_bspi(struct bcm_qspi *qspi)
236 return qspi->bspi_mode;
240 static inline bool bcm_qspi_has_fastbr(struct bcm_qspi *qspi)
242 if (!has_bspi(qspi) &&
243 ((qspi->mspi_maj_rev >= 1) &&
244 (qspi->mspi_min_rev >= 5)))
251 static inline bool bcm_qspi_has_sysclk_108(struct bcm_qspi *qspi)
253 if (!has_bspi(qspi) && (qspi->mspi_spcr3_sysclk ||
254 ((qspi->mspi_maj_rev >= 1) &&
255 (qspi->mspi_min_rev >= 6))))
261 static inline int bcm_qspi_spbr_min(struct bcm_qspi *qspi)
263 if (bcm_qspi_has_fastbr(qspi))
269 /* Read qspi controller register*/
270 static inline u32 bcm_qspi_read(struct bcm_qspi *qspi, enum base_type type,
273 return bcm_qspi_readl(qspi->big_endian, qspi->base[type] + offset);
276 /* Write qspi controller register*/
277 static inline void bcm_qspi_write(struct bcm_qspi *qspi, enum base_type type,
280 bcm_qspi_writel(qspi->big_endian, data, qspi->base[type] + offset);
284 static int bcm_qspi_bspi_busy_poll(struct bcm_qspi *qspi)
290 if (!(bcm_qspi_read(qspi, BSPI, BSPI_BUSY_STATUS) & 1))
294 dev_warn(&qspi->pdev->dev, "timeout waiting for !busy_status\n");
298 static inline bool bcm_qspi_bspi_ver_three(struct bcm_qspi *qspi)
300 if (qspi->bspi_maj_rev < 4)
305 static void bcm_qspi_bspi_flush_prefetch_buffers(struct bcm_qspi *qspi)
307 bcm_qspi_bspi_busy_poll(qspi);
309 bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 1);
310 bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 1);
311 bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0);
312 bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0);
315 static int bcm_qspi_bspi_lr_is_fifo_empty(struct bcm_qspi *qspi)
317 return (bcm_qspi_read(qspi, BSPI, BSPI_RAF_STATUS) &
321 static inline u32 bcm_qspi_bspi_lr_read_fifo(struct bcm_qspi *qspi)
323 u32 data = bcm_qspi_read(qspi, BSPI, BSPI_RAF_READ_DATA);
326 if (bcm_qspi_bspi_ver_three(qspi))
332 static inline void bcm_qspi_bspi_lr_start(struct bcm_qspi *qspi)
334 bcm_qspi_bspi_busy_poll(qspi);
335 bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL,
339 static inline void bcm_qspi_bspi_lr_clear(struct bcm_qspi *qspi)
341 bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL,
343 bcm_qspi_bspi_flush_prefetch_buffers(qspi);
346 static void bcm_qspi_bspi_lr_data_read(struct bcm_qspi *qspi)
348 u32 *buf = (u32 *)qspi->bspi_rf_op->data.buf.in;
351 dev_dbg(&qspi->pdev->dev, "xfer %p rx %p rxlen %d\n", qspi->bspi_rf_op,
352 qspi->bspi_rf_op->data.buf.in, qspi->bspi_rf_op_len);
353 while (!bcm_qspi_bspi_lr_is_fifo_empty(qspi)) {
354 data = bcm_qspi_bspi_lr_read_fifo(qspi);
355 if (likely(qspi->bspi_rf_op_len >= 4) &&
357 buf[qspi->bspi_rf_op_idx++] = data;
358 qspi->bspi_rf_op_len -= 4;
361 u8 *cbuf = (u8 *)&buf[qspi->bspi_rf_op_idx];
364 while (qspi->bspi_rf_op_len) {
367 qspi->bspi_rf_op_len--;
373 static void bcm_qspi_bspi_set_xfer_params(struct bcm_qspi *qspi, u8 cmd_byte,
376 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 0);
377 bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_CYCLE, bpc);
378 bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_PHASE, bpp);
379 bcm_qspi_write(qspi, BSPI, BSPI_CMD_AND_MODE_BYTE, cmd_byte);
380 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, flex_mode);
383 static int bcm_qspi_bspi_set_flex_mode(struct bcm_qspi *qspi,
392 dev_dbg(&qspi->pdev->dev, "set flex mode w %x addrlen %x hp %d\n",
424 bcm_qspi_bspi_set_xfer_params(qspi, command, bpp, bpc, flex_mode);
429 static int bcm_qspi_bspi_set_override(struct bcm_qspi *qspi,
434 u32 data = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
436 dev_dbg(&qspi->pdev->dev, "set override mode w %x addrlen %x hp %d\n",
468 bcm_qspi_write(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL, data);
469 bcm_qspi_bspi_set_xfer_params(qspi, op->cmd.opcode, 0, 0, 0);
474 static int bcm_qspi_bspi_set_mode(struct bcm_qspi *qspi,
482 qspi->xfer_mode.flex_mode = true;
484 if (!bcm_qspi_bspi_ver_three(qspi)) {
487 val = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
489 if (val & mask || qspi->s3_strap_override_ctrl & mask) {
490 qspi->xfer_mode.flex_mode = false;
491 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 0);
492 error = bcm_qspi_bspi_set_override(qspi, op, hp);
496 if (qspi->xfer_mode.flex_mode)
497 error = bcm_qspi_bspi_set_flex_mode(qspi, op, hp);
500 dev_warn(&qspi->pdev->dev,
503 } else if (qspi->xfer_mode.width != width ||
504 qspi->xfer_mode.addrlen != addrlen ||
505 qspi->xfer_mode.hp != hp) {
506 qspi->xfer_mode.width = width;
507 qspi->xfer_mode.addrlen = addrlen;
508 qspi->xfer_mode.hp = hp;
509 dev_dbg(&qspi->pdev->dev,
511 qspi->curr_cs,
512 qspi->xfer_mode.width,
513 qspi->xfer_mode.addrlen,
514 qspi->xfer_mode.hp != -1 ? ", hp mode" : "");
520 static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi)
522 if (!has_bspi(qspi))
525 qspi->bspi_enabled = 1;
526 if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1) == 0)
529 bcm_qspi_bspi_flush_prefetch_buffers(qspi);
531 bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 0);
535 static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi)
537 if (!has_bspi(qspi))
540 qspi->bspi_enabled = 0;
541 if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1))
544 bcm_qspi_bspi_busy_poll(qspi);
545 bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 1);
549 static void bcm_qspi_chip_select(struct bcm_qspi *qspi, int cs)
554 if (cs >= 0 && qspi->base[CHIP_SELECT]) {
555 rd = bcm_qspi_read(qspi, CHIP_SELECT, 0);
559 bcm_qspi_write(qspi, CHIP_SELECT, 0, wr);
563 dev_dbg(&qspi->pdev->dev, "using cs:%d\n", cs);
564 qspi->curr_cs = cs;
568 static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
574 spbr = qspi->base_clk / (2 * xp->speed_hz);
576 spcr = clamp_val(spbr, bcm_qspi_spbr_min(qspi), QSPI_SPBR_MAX);
577 bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spcr);
579 if (!qspi->mspi_maj_rev)
590 bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr);
592 if (bcm_qspi_has_fastbr(qspi)) {
598 if (bcm_qspi_has_sysclk_108(qspi)) {
601 qspi->base_clk = MSPI_BASE_FREQ * 4;
603 bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, 4);
606 bcm_qspi_write(qspi, MSPI, MSPI_SPCR3, spcr);
609 qspi->last_parms = *xp;
612 static void bcm_qspi_update_parms(struct bcm_qspi *qspi,
622 bcm_qspi_hw_set_parms(qspi, &xp);
650 static bool bcm_qspi_mspi_transfer_is_last(struct bcm_qspi *qspi,
654 spi_transfer_is_last(qspi->master, qt->trans))
660 static int update_qspi_trans_byte_count(struct bcm_qspi *qspi,
681 if (bcm_qspi_mspi_transfer_is_last(qspi, qt))
689 dev_dbg(&qspi->pdev->dev, "trans %p len %d byte %d ret %x\n",
694 static inline u8 read_rxram_slot_u8(struct bcm_qspi *qspi, int slot)
699 return bcm_qspi_read(qspi, MSPI, slot_offset) & 0xff;
702 static inline u16 read_rxram_slot_u16(struct bcm_qspi *qspi, int slot)
708 return (bcm_qspi_read(qspi, MSPI, lsb_offset) & 0xff) |
709 ((bcm_qspi_read(qspi, MSPI, msb_offset) & 0xff) << 8);
712 static void read_from_hw(struct bcm_qspi *qspi, int slots)
717 bcm_qspi_disable_bspi(qspi);
721 dev_err(&qspi->pdev->dev, "%s: too many slots!\n", __func__);
725 tp = qspi->trans_pos;
732 buf[tp.byte] = read_rxram_slot_u8(qspi, slot);
733 dev_dbg(&qspi->pdev->dev, "RD %02x\n",
739 buf[tp.byte / 2] = read_rxram_slot_u16(qspi,
741 dev_dbg(&qspi->pdev->dev, "RD %04x\n",
745 update_qspi_trans_byte_count(qspi, &tp,
749 qspi->trans_pos = tp;
752 static inline void write_txram_slot_u8(struct bcm_qspi *qspi, int slot,
758 bcm_qspi_write(qspi, MSPI, reg_offset, val);
761 static inline void write_txram_slot_u16(struct bcm_qspi *qspi, int slot,
768 bcm_qspi_write(qspi, MSPI, msb_offset, (val >> 8));
769 bcm_qspi_write(qspi, MSPI, lsb_offset, (val & 0xff));
772 static inline u32 read_cdram_slot(struct bcm_qspi *qspi, int slot)
774 return bcm_qspi_read(qspi, MSPI, MSPI_CDRAM + (slot << 2));
777 static inline void write_cdram_slot(struct bcm_qspi *qspi, int slot, u32 val)
779 bcm_qspi_write(qspi, MSPI, (MSPI_CDRAM + (slot << 2)), val);
783 static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi)
789 bcm_qspi_disable_bspi(qspi);
790 tp = qspi->trans_pos;
791 bcm_qspi_update_parms(qspi, spi, tp.trans);
799 write_txram_slot_u8(qspi, slot, val);
800 dev_dbg(&qspi->pdev->dev, "WR %02x\n", val);
805 write_txram_slot_u16(qspi, slot, val);
806 dev_dbg(&qspi->pdev->dev, "WR %04x\n", val);
810 if (has_bspi(qspi))
819 write_cdram_slot(qspi, slot, mspi_cdram);
821 tstatus = update_qspi_trans_byte_count(qspi, &tp,
827 dev_err(&qspi->pdev->dev, "%s: no data to send?", __func__);
831 dev_dbg(&qspi->pdev->dev, "submitting %d slots\n", slot);
832 bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
833 bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1);
845 mspi_cdram = read_cdram_slot(qspi, slot - 1) &
847 write_cdram_slot(qspi, slot - 1, mspi_cdram);
850 if (has_bspi(qspi))
851 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 1);
856 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0xe0);
865 struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
869 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
871 if (bcm_qspi_bspi_ver_three(qspi))
877 bcm_qspi_chip_select(qspi, spi->chip_select);
878 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
884 if (bcm_qspi_bspi_ver_three(qspi) == false) {
886 bcm_qspi_write(qspi, BSPI,
890 if (!qspi->xfer_mode.flex_mode)
895 if (bcm_qspi_bspi_ver_three(qspi) == true)
903 qspi->bspi_rf_op_idx = 0;
911 reinit_completion(&qspi->bspi_done);
912 bcm_qspi_enable_bspi(qspi);
914 qspi->bspi_rf_op = op;
915 qspi->bspi_rf_op_status = 0;
916 qspi->bspi_rf_op_len = rdlen;
917 dev_dbg(&qspi->pdev->dev,
919 bcm_qspi_write(qspi, BSPI, BSPI_RAF_START_ADDR, addr);
920 bcm_qspi_write(qspi, BSPI, BSPI_RAF_NUM_WORDS, len_words);
921 bcm_qspi_write(qspi, BSPI, BSPI_RAF_WATERMARK, 0);
922 if (qspi->soc_intc) {
933 bcm_qspi_bspi_lr_start(qspi);
934 if (!wait_for_completion_timeout(&qspi->bspi_done, timeo)) {
935 dev_err(&qspi->pdev->dev, "timeout waiting for BSPI\n");
952 struct bcm_qspi *qspi = spi_master_get_devdata(master);
957 bcm_qspi_chip_select(qspi, spi->chip_select);
958 qspi->trans_pos.trans = trans;
959 qspi->trans_pos.byte = 0;
961 while (qspi->trans_pos.byte < trans->len) {
962 reinit_completion(&qspi->mspi_done);
964 slots = write_to_hw(qspi, spi);
965 if (!wait_for_completion_timeout(&qspi->mspi_done, timeo)) {
966 dev_err(&qspi->pdev->dev, "timeout waiting for MSPI\n");
970 read_from_hw(qspi, slots);
972 bcm_qspi_enable_bspi(qspi);
981 struct bcm_qspi *qspi = spi_master_get_devdata(master);
1000 qspi->trans_pos.mspi_last_trans = false;
1004 qspi->trans_pos.mspi_last_trans = true;
1021 struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
1035 if (has_bspi(qspi) && bcm_qspi_bspi_ver_three(qspi) == true) {
1054 if (!has_bspi(qspi) || mspi_read)
1057 ret = bcm_qspi_bspi_set_mode(qspi, op, 0);
1075 struct bcm_qspi *qspi = qspi_dev_id->dev;
1076 u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
1079 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1082 bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status);
1083 if (qspi->soc_intc)
1085 complete(&qspi->mspi_done);
1095 struct bcm_qspi *qspi = qspi_dev_id->dev;
1096 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1099 if (qspi->bspi_enabled && qspi->bspi_rf_op) {
1100 bcm_qspi_bspi_lr_data_read(qspi);
1101 if (qspi->bspi_rf_op_len == 0) {
1102 qspi->bspi_rf_op = NULL;
1103 if (qspi->soc_intc) {
1111 if (qspi->bspi_rf_op_status)
1112 bcm_qspi_bspi_lr_clear(qspi);
1114 bcm_qspi_bspi_flush_prefetch_buffers(qspi);
1117 if (qspi->soc_intc)
1123 if (qspi->bspi_enabled && status && qspi->bspi_rf_op_len == 0)
1124 complete(&qspi->bspi_done);
1132 struct bcm_qspi *qspi = qspi_dev_id->dev;
1133 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1135 dev_err(&qspi->pdev->dev, "BSPI INT error\n");
1136 qspi->bspi_rf_op_status = -EIO;
1137 if (qspi->soc_intc)
1141 complete(&qspi->bspi_done);
1148 struct bcm_qspi *qspi = qspi_dev_id->dev;
1149 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1214 static void bcm_qspi_bspi_init(struct bcm_qspi *qspi)
1218 val = bcm_qspi_read(qspi, BSPI, BSPI_REVISION_ID);
1219 qspi->bspi_maj_rev = (val >> 8) & 0xff;
1220 qspi->bspi_min_rev = val & 0xff;
1221 if (!(bcm_qspi_bspi_ver_three(qspi))) {
1223 bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_VALUE, 0);
1224 bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_ENABLE, 1);
1226 qspi->bspi_enabled = 1;
1227 bcm_qspi_disable_bspi(qspi);
1228 bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0);
1229 bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0);
1232 static void bcm_qspi_hw_init(struct bcm_qspi *qspi)
1236 bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 0);
1237 bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_MSB, 0);
1238 bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
1239 bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, 0);
1240 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0x20);
1244 parms.speed_hz = qspi->max_speed_hz;
1245 bcm_qspi_hw_set_parms(qspi, &parms);
1247 if (has_bspi(qspi))
1248 bcm_qspi_bspi_init(qspi);
1251 static void bcm_qspi_hw_uninit(struct bcm_qspi *qspi)
1253 u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
1255 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0);
1256 if (has_bspi(qspi))
1257 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
1260 bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status & ~1);
1289 .compatible = "brcm,spi-bcm7445-qspi",
1294 .compatible = "brcm,spi-bcm-qspi",
1298 .compatible = "brcm,spi-bcm7216-qspi",
1302 .compatible = "brcm,spi-bcm7278-qspi",
1315 struct bcm_qspi *qspi;
1340 qspi = spi_master_get_devdata(master);
1342 qspi->clk = devm_clk_get_optional(&pdev->dev, NULL);
1343 if (IS_ERR(qspi->clk))
1344 return PTR_ERR(qspi->clk);
1346 qspi->pdev = pdev;
1347 qspi->trans_pos.trans = NULL;
1348 qspi->trans_pos.byte = 0;
1349 qspi->trans_pos.mspi_last_trans = true;
1350 qspi->master = master;
1362 qspi->big_endian = of_device_is_big_endian(dev->of_node);
1372 qspi->base[MSPI] = devm_ioremap_resource(dev, res);
1373 if (IS_ERR(qspi->base[MSPI]))
1374 return PTR_ERR(qspi->base[MSPI]);
1378 qspi->base[BSPI] = devm_ioremap_resource(dev, res);
1379 if (IS_ERR(qspi->base[BSPI]))
1380 return PTR_ERR(qspi->base[BSPI]);
1381 qspi->bspi_mode = true;
1383 qspi->bspi_mode = false;
1386 dev_info(dev, "using %smspi mode\n", qspi->bspi_mode ? "bspi-" : "");
1390 qspi->base[CHIP_SELECT] = devm_ioremap_resource(dev, res);
1391 if (IS_ERR(qspi->base[CHIP_SELECT]))
1392 return PTR_ERR(qspi->base[CHIP_SELECT]);
1395 qspi->dev_ids = kcalloc(num_irqs, sizeof(struct bcm_qspi_dev_id),
1397 if (!qspi->dev_ids)
1405 qspi->soc_intc = soc_intc;
1408 qspi->soc_intc = NULL;
1411 if (qspi->clk) {
1412 ret = clk_prepare_enable(qspi->clk);
1417 qspi->base_clk = clk_get_rate(qspi->clk);
1419 qspi->base_clk = MSPI_BASE_FREQ;
1423 rev = bcm_qspi_read(qspi, MSPI, MSPI_REV);
1429 qspi->mspi_maj_rev = (rev >> 4) & 0xf;
1430 qspi->mspi_min_rev = rev & 0xf;
1431 qspi->mspi_spcr3_sysclk = data->has_spcr3_sysclk;
1433 qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2);
1439 bcm_qspi_hw_uninit(qspi);
1456 &qspi->dev_ids[val]);
1462 qspi->dev_ids[val].dev = qspi;
1463 qspi->dev_ids[val].irqp = &qspi_irq_tab[val];
1477 bcm_qspi_hw_init(qspi);
1478 init_completion(&qspi->mspi_done);
1479 init_completion(&qspi->bspi_done);
1480 qspi->curr_cs = -1;
1482 platform_set_drvdata(pdev, qspi);
1484 qspi->xfer_mode.width = -1;
1485 qspi->xfer_mode.addrlen = -1;
1486 qspi->xfer_mode.hp = -1;
1497 bcm_qspi_hw_uninit(qspi);
1499 clk_disable_unprepare(qspi->clk);
1501 kfree(qspi->dev_ids);
1509 struct bcm_qspi *qspi = platform_get_drvdata(pdev);
1511 spi_unregister_master(qspi->master);
1512 bcm_qspi_hw_uninit(qspi);
1513 clk_disable_unprepare(qspi->clk);
1514 kfree(qspi->dev_ids);
1523 struct bcm_qspi *qspi = dev_get_drvdata(dev);
1526 if (!bcm_qspi_bspi_ver_three(qspi))
1527 qspi->s3_strap_override_ctrl =
1528 bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
1530 spi_master_suspend(qspi->master);
1531 clk_disable_unprepare(qspi->clk);
1532 bcm_qspi_hw_uninit(qspi);
1539 struct bcm_qspi *qspi = dev_get_drvdata(dev);
1542 bcm_qspi_hw_init(qspi);
1543 bcm_qspi_chip_select(qspi, qspi->curr_cs);
1544 if (qspi->soc_intc)
1546 qspi->soc_intc->bcm_qspi_int_set(qspi->soc_intc, MSPI_DONE,
1549 ret = clk_prepare_enable(qspi->clk);
1551 spi_master_resume(qspi->master);