Lines Matching defs:MSPI
83 /* MSPI register offsets */
170 MSPI,
567 /* MSPI helpers */
577 bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spcr);
590 bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr);
603 bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, 4);
606 bcm_qspi_write(qspi, MSPI, MSPI_SPCR3, spcr);
699 return bcm_qspi_read(qspi, MSPI, slot_offset) & 0xff;
708 return (bcm_qspi_read(qspi, MSPI, lsb_offset) & 0xff) |
709 ((bcm_qspi_read(qspi, MSPI, msb_offset) & 0xff) << 8);
758 bcm_qspi_write(qspi, MSPI, reg_offset, val);
768 bcm_qspi_write(qspi, MSPI, msb_offset, (val >> 8));
769 bcm_qspi_write(qspi, MSPI, lsb_offset, (val & 0xff));
774 return bcm_qspi_read(qspi, MSPI, MSPI_CDRAM + (slot << 2));
779 bcm_qspi_write(qspi, MSPI, (MSPI_CDRAM + (slot << 2)), val);
832 bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
833 bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1);
851 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 1);
853 /* Must flush previous writes before starting MSPI operation */
856 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0xe0);
878 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
924 * clear soc MSPI and BSPI interrupts and enable
966 dev_err(&qspi->pdev->dev, "timeout waiting for MSPI\n");
1040 * using MSPI.
1049 /* non-aligned and very short transfers are handled by MSPI */
1076 u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
1082 bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status);
1236 bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 0);
1237 bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_MSB, 0);
1238 bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
1239 bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, 0);
1240 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0x20);
1253 u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
1255 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0);
1257 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
1260 bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status & ~1);
1372 qspi->base[MSPI] = devm_ioremap_resource(dev, res);
1373 if (IS_ERR(qspi->base[MSPI]))
1374 return PTR_ERR(qspi->base[MSPI]);
1423 rev = bcm_qspi_read(qspi, MSPI, MSPI_REV);
1545 /* enable MSPI interrupt */