Lines Matching refs:hw
52 void (*rx_word)(struct au1550_spi *hw);
53 void (*tx_word)(struct au1550_spi *hw);
55 irqreturn_t (*irq_callback)(struct au1550_spi *hw);
90 static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw);
102 static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned speed_hz)
104 u32 mainclk_hz = hw->pdata->mainclk_hz;
125 static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw)
127 hw->regs->psc_spimsk =
133 hw->regs->psc_spievent =
140 static void au1550_spi_reset_fifos(struct au1550_spi *hw)
144 hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC;
147 pcr = hw->regs->psc_spipcr;
163 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
169 if (hw->pdata->deactivate_cs)
170 hw->pdata->deactivate_cs(hw->pdata, spi->chip_select,
175 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
177 cfg = hw->regs->psc_spicfg;
179 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
196 if (hw->usedma && spi->bits_per_word <= 8)
205 cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz);
207 hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE;
210 stat = hw->regs->psc_spistat;
214 if (hw->pdata->activate_cs)
215 hw->pdata->activate_cs(hw->pdata, spi->chip_select,
223 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
238 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
240 cfg = hw->regs->psc_spicfg;
242 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
245 if (hw->usedma && bpw <= 8)
254 cfg |= au1550_spi_baudcfg(hw, hz);
256 hw->regs->psc_spicfg = cfg;
261 stat = hw->regs->psc_spistat;
266 au1550_spi_reset_fifos(hw);
267 au1550_spi_mask_ack_all(hw);
279 static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned size)
281 hw->dma_rx_tmpbuf = kmalloc(size, GFP_KERNEL);
282 if (!hw->dma_rx_tmpbuf)
284 hw->dma_rx_tmpbuf_size = size;
285 hw->dma_rx_tmpbuf_addr = dma_map_single(hw->dev, hw->dma_rx_tmpbuf,
287 if (dma_mapping_error(hw->dev, hw->dma_rx_tmpbuf_addr)) {
288 kfree(hw->dma_rx_tmpbuf);
289 hw->dma_rx_tmpbuf = 0;
290 hw->dma_rx_tmpbuf_size = 0;
296 static void au1550_spi_dma_rxtmp_free(struct au1550_spi *hw)
298 dma_unmap_single(hw->dev, hw->dma_rx_tmpbuf_addr,
299 hw->dma_rx_tmpbuf_size, DMA_FROM_DEVICE);
300 kfree(hw->dma_rx_tmpbuf);
301 hw->dma_rx_tmpbuf = 0;
302 hw->dma_rx_tmpbuf_size = 0;
307 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
312 hw->len = t->len;
313 hw->tx_count = 0;
314 hw->rx_count = 0;
316 hw->tx = t->tx_buf;
317 hw->rx = t->rx_buf;
331 dma_tx_addr = dma_map_single(hw->dev,
334 if (dma_mapping_error(hw->dev, dma_tx_addr))
335 dev_err(hw->dev, "tx dma map error\n");
341 dma_rx_addr = dma_map_single(hw->dev,
344 if (dma_mapping_error(hw->dev, dma_rx_addr))
345 dev_err(hw->dev, "rx dma map error\n");
348 if (t->len > hw->dma_rx_tmpbuf_size) {
351 au1550_spi_dma_rxtmp_free(hw);
352 ret = au1550_spi_dma_rxtmp_alloc(hw, max(t->len,
357 hw->rx = hw->dma_rx_tmpbuf;
358 dma_rx_addr = hw->dma_rx_tmpbuf_addr;
359 dma_sync_single_for_device(hw->dev, dma_rx_addr,
364 dma_sync_single_for_device(hw->dev, dma_rx_addr,
366 hw->tx = hw->rx;
370 res = au1xxx_dbdma_put_dest(hw->dma_rx_ch, virt_to_phys(hw->rx),
373 dev_err(hw->dev, "rx dma put dest error\n");
375 res = au1xxx_dbdma_put_source(hw->dma_tx_ch, virt_to_phys(hw->tx),
378 dev_err(hw->dev, "tx dma put source error\n");
380 au1xxx_dbdma_start(hw->dma_rx_ch);
381 au1xxx_dbdma_start(hw->dma_tx_ch);
384 hw->regs->psc_spimsk = PSC_SPIMSK_SD;
388 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
391 wait_for_completion(&hw->master_done);
393 au1xxx_dbdma_stop(hw->dma_tx_ch);
394 au1xxx_dbdma_stop(hw->dma_rx_ch);
398 dma_sync_single_for_cpu(hw->dev, dma_rx_addr, t->len,
403 dma_unmap_single(hw->dev, dma_rx_addr, t->len,
406 dma_unmap_single(hw->dev, dma_tx_addr, t->len,
409 return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
412 static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw)
416 stat = hw->regs->psc_spistat;
417 evnt = hw->regs->psc_spievent;
420 dev_err(hw->dev, "Unexpected IRQ!\n");
433 au1550_spi_mask_ack_all(hw);
434 au1xxx_dbdma_stop(hw->dma_rx_ch);
435 au1xxx_dbdma_stop(hw->dma_tx_ch);
438 hw->rx_count = hw->len - au1xxx_get_dma_residue(hw->dma_rx_ch);
439 hw->tx_count = hw->len - au1xxx_get_dma_residue(hw->dma_tx_ch);
441 au1xxx_dbdma_reset(hw->dma_rx_ch);
442 au1xxx_dbdma_reset(hw->dma_tx_ch);
443 au1550_spi_reset_fifos(hw);
446 dev_err(hw->dev,
449 dev_err(hw->dev,
453 complete(&hw->master_done);
459 au1550_spi_mask_ack_all(hw);
460 hw->rx_count = hw->len;
461 hw->tx_count = hw->len;
462 complete(&hw->master_done);
470 static void au1550_spi_rx_word_##size(struct au1550_spi *hw) \
472 u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask); \
474 if (hw->rx) { \
475 *(u##size *)hw->rx = (u##size)fifoword; \
476 hw->rx += (size) / 8; \
478 hw->rx_count += (size) / 8; \
482 static void au1550_spi_tx_word_##size(struct au1550_spi *hw) \
485 if (hw->tx) { \
486 fifoword = *(u##size *)hw->tx & (u32)(mask); \
487 hw->tx += (size) / 8; \
489 hw->tx_count += (size) / 8; \
490 if (hw->tx_count >= hw->len) \
492 hw->regs->psc_spitxrx = fifoword; \
506 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
508 hw->tx = t->tx_buf;
509 hw->rx = t->rx_buf;
510 hw->len = t->len;
511 hw->tx_count = 0;
512 hw->rx_count = 0;
518 while (hw->tx_count < hw->len) {
520 hw->tx_word(hw);
522 if (hw->tx_count >= hw->len) {
527 stat = hw->regs->psc_spistat;
534 hw->regs->psc_spimsk = mask;
538 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
541 wait_for_completion(&hw->master_done);
543 return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
546 static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
551 stat = hw->regs->psc_spistat;
552 evnt = hw->regs->psc_spievent;
555 dev_err(hw->dev, "Unexpected IRQ!\n");
567 au1550_spi_mask_ack_all(hw);
568 au1550_spi_reset_fifos(hw);
569 dev_err(hw->dev,
572 complete(&hw->master_done);
582 stat = hw->regs->psc_spistat;
594 if (!(stat & PSC_SPISTAT_RE) && hw->rx_count < hw->len) {
595 hw->rx_word(hw);
598 if (!(stat & PSC_SPISTAT_TF) && hw->tx_count < hw->len)
599 hw->tx_word(hw);
603 hw->regs->psc_spievent = PSC_SPIEVNT_RR | PSC_SPIEVNT_TR;
622 hw->regs->psc_spievent = PSC_SPIEVNT_TU | PSC_SPIEVNT_MD;
624 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
628 if (hw->rx_count >= hw->len) {
630 au1550_spi_mask_ack_all(hw);
631 complete(&hw->master_done);
638 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
639 return hw->txrx_bufs(spi, t);
644 struct au1550_spi *hw = dev;
645 return hw->irq_callback(hw);
648 static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw)
651 if (hw->usedma) {
652 hw->txrx_bufs = &au1550_spi_dma_txrxb;
653 hw->irq_callback = &au1550_spi_dma_irq_callback;
655 hw->rx_word = &au1550_spi_rx_word_8;
656 hw->tx_word = &au1550_spi_tx_word_8;
657 hw->txrx_bufs = &au1550_spi_pio_txrxb;
658 hw->irq_callback = &au1550_spi_pio_irq_callback;
661 hw->rx_word = &au1550_spi_rx_word_16;
662 hw->tx_word = &au1550_spi_tx_word_16;
663 hw->txrx_bufs = &au1550_spi_pio_txrxb;
664 hw->irq_callback = &au1550_spi_pio_irq_callback;
666 hw->rx_word = &au1550_spi_rx_word_32;
667 hw->tx_word = &au1550_spi_tx_word_32;
668 hw->txrx_bufs = &au1550_spi_pio_txrxb;
669 hw->irq_callback = &au1550_spi_pio_irq_callback;
673 static void au1550_spi_setup_psc_as_spi(struct au1550_spi *hw)
678 hw->regs->psc_ctrl = PSC_CTRL_DISABLE;
680 hw->regs->psc_sel = PSC_SEL_PS_SPIMODE;
683 hw->regs->psc_spicfg = 0;
686 hw->regs->psc_ctrl = PSC_CTRL_ENABLE;
690 stat = hw->regs->psc_spistat;
695 cfg = hw->usedma ? 0 : PSC_SPICFG_DD_DISABLE;
705 hw->regs->psc_spicfg = cfg;
708 au1550_spi_mask_ack_all(hw);
710 hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE;
714 stat = hw->regs->psc_spistat;
718 au1550_spi_reset_fifos(hw);
724 struct au1550_spi *hw;
740 hw = spi_master_get_devdata(master);
742 hw->master = master;
743 hw->pdata = dev_get_platdata(&pdev->dev);
744 hw->dev = &pdev->dev;
746 if (hw->pdata == NULL) {
758 hw->irq = r->start;
760 hw->usedma = 0;
763 hw->dma_tx_id = r->start;
766 hw->dma_rx_id = r->start;
771 hw->usedma = 1;
783 hw->ioarea = request_mem_region(r->start, sizeof(psc_spi_t),
785 if (!hw->ioarea) {
791 hw->regs = (psc_spi_t __iomem *)ioremap(r->start, sizeof(psc_spi_t));
792 if (!hw->regs) {
798 platform_set_drvdata(pdev, hw);
800 init_completion(&hw->master_done);
802 hw->bitbang.master = hw->master;
803 hw->bitbang.setup_transfer = au1550_spi_setupxfer;
804 hw->bitbang.chipselect = au1550_spi_chipsel;
805 hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs;
807 if (hw->usedma) {
808 hw->dma_tx_ch = au1xxx_dbdma_chan_alloc(ddma_memid,
809 hw->dma_tx_id, NULL, (void *)hw);
810 if (hw->dma_tx_ch == 0) {
816 au1xxx_dbdma_set_devwidth(hw->dma_tx_ch, 8);
817 if (au1xxx_dbdma_ring_alloc(hw->dma_tx_ch,
826 hw->dma_rx_ch = au1xxx_dbdma_chan_alloc(hw->dma_rx_id,
827 ddma_memid, NULL, (void *)hw);
828 if (hw->dma_rx_ch == 0) {
834 au1xxx_dbdma_set_devwidth(hw->dma_rx_ch, 8);
835 if (au1xxx_dbdma_ring_alloc(hw->dma_rx_ch,
843 err = au1550_spi_dma_rxtmp_alloc(hw,
852 au1550_spi_bits_handlers_set(hw, 8);
854 err = request_irq(hw->irq, au1550_spi_irq, 0, pdev->name, hw);
861 master->num_chipselect = hw->pdata->num_chipselect;
875 master->max_speed_hz = hw->pdata->mainclk_hz / min_div;
877 hw->pdata->mainclk_hz / (max_div + 1) + 1;
880 au1550_spi_setup_psc_as_spi(hw);
882 err = spi_bitbang_start(&hw->bitbang);
895 free_irq(hw->irq, hw);
898 au1550_spi_dma_rxtmp_free(hw);
902 if (hw->usedma)
903 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
907 if (hw->usedma)
908 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
911 iounmap((void __iomem *)hw->regs);
918 spi_master_put(hw->master);
926 struct au1550_spi *hw = platform_get_drvdata(pdev);
929 hw->master->bus_num);
931 spi_bitbang_stop(&hw->bitbang);
932 free_irq(hw->irq, hw);
933 iounmap((void __iomem *)hw->regs);
934 release_mem_region(hw->ioarea->start, sizeof(psc_spi_t));
936 if (hw->usedma) {
937 au1550_spi_dma_rxtmp_free(hw);
938 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
939 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
942 spi_master_put(hw->master);